Week In Review: IoT, Security, Autos


AI/Edge Vastai Technologies is using Arteris IP’s FlexNoC Interconnect IP and AI Package for its Artificial Intelligence Chips for artificial intelligence and computer vision systems-on-chip (SoCs). Startup Vastai Technologies was founded in December 2018, designs ASICs and software platforms for computer vision and AI applications, such as smart city, smart surveillance, smart education, ac... » read more

A UFS Verification Closure Flow Using The Synopsys Verification Continuum Platform


It's a longstanding cliche, but it is true that “there is no silver bullet for functional verification.” No single tool or methodology can find and shoot down all the bugs in a large, complex semiconductor design. Simulation is well understood but can be slow for today's large SoCs. Emulation hardware is fast, but expensive enough that it is usually shared across a verification team. Formal... » read more

CXL Vs. CCIX


Kurt Shuler, vice president of marketing at ArterisIP, explains how these two standards differ, which one works best where, and what each was designed for. » read more

Verdi Transaction Debug Solution: Unified Performance Analysis And Debug For Interconnect


In modern systems on chip (SoCs), where Arm AMBA protocols are intensively used as standard intellectual property (IP) interfaces, the interconnect is usually required to bridge and facilitate the communication between many different IP interfaces. The interconnect presents one of the biggest challenges of SoC verification, considering the different kinds of protocol interfaces, conversion of d... » read more

ML, Edge Drive IP To Outperform Broader Chip Market


The market for third-party semiconductor IP is surging, spurred by the need for more specific capabilities across a wide variety of markets. While the IP industry is not immune to steep market declines in semiconductor industry, it does have more built-in resilience than other parts of the industry. Case in point: The top 15 semiconductor suppliers were hit with an 18% decline in 2019 first-... » read more

Assuring the Integrity of RISC-V Cores and SoCs


The open RISC-V processor architecture is shaking up the intellectual property (IP) and system-on-chip (SoC) worlds. There is great interest and much industry activity underway. However, successful RISC-V core providers will have to verify all aspects of integrity for their designs: functional correctness, safety, security, and trust. SOC developers evaluating potential RISC-V need to check tha... » read more

Multiphysics Simulations For RFICs And SoCs For 5G Applications


System-on-chips (SoCs) and radio frequency integrated circuits (RFICs) for 5G smartphones and networks need to manage huge amounts of antenna data and offer significantly high processing capabilities in thermally and power-constrained environments. ANSYS multiphysics simulations simultaneously solve power, thermal, variability, timing, electromagnetics and reliability challenges across the spec... » read more

Week in Review: IoT, Security, Auto


Products/Services Arteris IP reports that Bitmain licensed the Arteris Ncore Cache Coherent Interconnect intellectual property for use in its next-generation Sophon Tensor Processing Unit system-on-a-chip devices for the scalable hardware acceleration of artificial intelligence and machine learning algorithms. “Our choice of interconnect IP became more important as we continued to increase t... » read more

Security’s Very Strange Path To Success


Security at the chip level appears to be heading toward a more promising future. The reason is simple—more people are willing to pay for security than in the past. For the most part, security is like insurance. You don't know it's working until something goes wrong, and you don't necessarily even know right away if there has been a breach. Sometimes it takes years to show up, because it ca... » read more

In-Chip Monitoring Becoming Essential Below 10nm


Rising systemic complexity and more potential interactions in heterogeneous designs is making it much more difficult to ensure a chip, or even a block within a chip, will functioning properly without actually monitoring that behavior in real-time. Continuous and sporadic monitoring have been creeping into designs for the past couple of decades. But it hasn’t always been clear how effective... » read more

← Older posts