Systems & Design

Radiation Tolerance Is Not Just For Rocket Scientists

Mitigating digital logic soft errors in the terrestrial environment.


As technology scales, soft errors from particle radiation are becoming increasingly concerning for in-field reliability. These radiation effects are called Single Event Upsets (SEU) and the frequency of the failures due to SEUs is known as the Soft Error Rate (SER). Soft errors are failures due to external sources. By contrast, hard errors refer to actual process manufacturing defects or electromigration defects that get formed during circuit operation. Hard errors cannot be fixed without changing the silicon; soft errors are usually temporary, and the circuit subsequently returns to functionality.

In older technologies, this SEU problem was limited to radiation-hostile environments such as space. With technologies scaling to smaller geometries, and with the increased number of elements integrated into a system-on-chip (SoC), every component in an SoC is now susceptible to particle radiation. Therefore, the SoC overall has a higher probability of suffering from SEUs. Of the various SoC components, SRAMs and standard-cell sequential elements could experience data upset. Similarly, combinational circuits could experience soft delay errors or glitches which may impact the timing and/or functionality of the SoC and eventually cause data failure. This translates into the possibility of a higher SER for smaller geometry SoCs, and this effect needs to be considered in designs for high-reliability applications like Automotive, Datacenter & High-Performance Computing.

In this paper, we will:

  • Review the types of radiation particles and the sources of radiation that impact circuit SER
  • Address the techniques to mitigate terrestrial radiation impact in SoC design for high-reliability applications such as Automotive and Datacenter
  • Discuss the impact of technology scaling from planar to finFET on SoC reliability due to the SER effect
  • Describe how Synopsys logic libraries are SEU-optimized while still meeting the stringent power, performance, and area (PPA) requirements of finFET SoCs

To read more, click here.

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