Tech Talk: 5/3nm Parasitics


Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

New Nodes, Materials, Memories


Ellie Yieh, vice president and general manager of Advanced Product Technology Development at [getentity id="22817" e_name="Applied Materials"], and head of the company's Maydan Technology Center, sat down with Semiconductor Engineering to talk about challenges, changes and solutions at advanced nodes and with new applications. What follows are excerpts of that conversation. SE: How far can w... » read more

Chip Aging Accelerates


Reliability is becoming an increasingly important proof point for new chips as they are rolled out in new markets such as automotive, cloud computing and industrial IoT, but actually proving that a chip will function as expected over time is becoming much more difficult. In the past, reliability generally was considered a foundry issue. Chips developed for computers and phones were designed ... » read more

New Thermal Issues Emerge


Thermal monitoring is becoming more critical as gate density continues to increase at each new node and as chips are developed for safety critical markets such as automotive. This may sound counterintuitive because the whole point of device scaling is to increase gate density. But at 10/7 and 7/5nm, static current leakage is becoming a bigger issue, raising questions about how long [getkc id... » read more

7/5nm Timing Closure Intensifies


Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

Nodes Vs. Nodelets


Foundries are flooding the market with new nodes and different process options at existing nodes, spreading confusion and creating a variety of challenges for chipmakers. There are full-node processes, such as 10nm and 7nm, with 5nm and 3nm in R&D. But there also is an increasing number of half-nodes or "node-lets" being introduced, including 12nm, 11nm, 8nm, 6nm and 4nm. Node-lets ar... » read more

The Future Of FinFETs


The number of questions about finFETs is increasing—particularly, how long can they continue to be used before some version of gate-all-around FET is required to replace them. This discussion is confusing in many respects. For one thing, a 7nm finFET for TSMC or Samsung is not the same as a 7nm finFET for Intel or GlobalFoundries. There are a bunch of other nodes being proposed, as well, i... » read more

E-beam Inspection Makes Inroads


E-beam inspection is gaining traction in critical areas in fab production as it is becoming more difficult to find tiny defects with traditional methods at advanced nodes. Applied Materials, ASML/HMI and others are developing new e-beam inspection tools and/or techniques to solve some of the more difficult defect issues in the fab. [gettech id="31057" t_name="E-beam"] inspection is one of tw... » read more

Follow The Moving Money


Semiconductor economics are changing by market, by region, and by product node and packaging type, adding new complexity into decisions about which technology to use for which products and why. Money is the common denominator in all of these decisions, whether it's measured by return on invested capital, quarterly profits, or long-term investments that can include acquisitions, organic growt... » read more

Tech Talk: 7nm Process Variation


Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

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