More Data, More Processing, More Chips


Simon Segars, CEO of Arm, sat down with Semiconductor Engineering to talk about the impact of heterogeneous computing and new packaging approaches on IP, the need for more security, and how 5G and the edge will impact compute architectures and the chip industry. SE: There are a whole bunch of new markets opening up. How does Arm plan to tackle those? Segars: Luckily for us, we can design ... » read more

Stacking Memory On Logic, Take Two


True 3D-ICs, where a memory die is stacked on top of a logic die using through-silicon vias, appear to be gaining momentum. There are a couple reasons why this is happening, and a handful of issues that need to be considered before even seriously considering this option. None of this is easy. On a scale of 1 to 10, this ranks somewhere around 9.99, in part because the EDA tools needed to rem... » read more

Another Brick Or Two In The Chip Design Wall


Physical challenges come and go in the semiconductor world. But increasingly, they also stick around, showing up in inconvenient places at the worst time. The chip industry has confronted and solved some massive challenges over the years. There was the 1 micron lithography wall, which was supposed to be impenetrable. That was followed by the 193nm litho challenge, which cost many billions of... » read more

Nvidia’s Top Technologists Discuss The Future Of GPUs


Semiconductor Engineering sat down to discuss the role of the GPU in artificial intelligence, autonomous and assisted driving, advanced packaging and heterogeneous architectures with Bill Dally, Nvidia’s chief scientist, and Jonah Alben, senior vice president of Nvidia’s GPU engineering, at IEEE’s Hot Chips 2019 conference. What follows are excerpts of that conversation. SE: There are ... » read more

IP’s Growing Impact On Yield And Reliability


Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

Signoff-Compatible CDC


Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced nodes and in AI chips, and why dealing with CDC effectively is becoming a competitive requirement for performance and low power. » read more

Node Within A Node


Enough margin exists in manufacturing processes to carve out the equivalent of a full node of scaling, but shrinking that margin will require a collective push across the entire semiconductor manufacturing supply chain. Margin is built into manufacturing at various stages to ensure that chips are manufacturable and yield sufficiently. It can include everything from variation in how lines are... » read more

Test Chips Play Larger Role At Advanced Nodes


Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long b... » read more

CEO Outlook: Rising Costs, Chiplets, And A Trade War


Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

5nm Vs. 3nm


Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between. The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm ... » read more

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