tag: interconnects

Research Bits: Jan. 20
By Jesse Allen - 20 Jan, 2026 - Comments: 0

ALD for Ru wiring Researchers from Ulsan National Institute of Science and Technology (UNIST), Hongik University, and Tanaka Precious Metal Technologies developed an atomic layer deposition (ALD) process for creating chip interconnects using a ruthenium (Ru) precursor with a thermal stability up to 400 °C. The high-temperature ALD process can produce dense, high-quality Ru films without deg... » read more

Shaping The Future Of AI Processors: A Tech Threads Conversation With Jim Keller
By Nandan Nayampally - 25 Nov, 2025 - Comments: 0

I had the pleasure of hosting renowned computer architect and Tenstorrent CEO Jim Keller, on the latest episode of Baya Systems’ Tech Threads podcast. If you haven’t already, listen to get his insights on the need for “open” intelligence architectures and what would be needed to drive the semiconductor industry forward. What is an “open” intelligent architecture and ecosystem? As... » read more

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts
By Reela Samuel - 25 Nov, 2025 - Comments: 0

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher power density, routing congestion, and reduced yield. Three-dimensional integrated circuits (3D-IC) technology represents a breakthrough approach by stacking multiple dies vertically. This design red... » read more

From Bottleneck to Breakthrough: Scalable Fabric IP for High- Bandwidth AI and HPC Systems
By Baya Systems - 24 Nov, 2025 - Comments: 0

As compute density and heterogeneity grow rapidly in modern SoCs targeting high-performance computing (HPC) and artificial intelligence (AI) workloads, efficient data movement has emerged as a critical performance and power bottleneck. With increasing core counts, high-speed accelerators, and complex memory hierarchies, traditional bus and crossbar-based interconnects fail to scale, resulting i... » read more

New Interconnect Materials Beyond Copper (Florida State Univ., Cornell)
By Technical Paper Link - 14 Nov, 2025 - Comments: 0

A new technical paper titled "Shrinking interconnects beyond copper" was published by researchers at Florida State University and Cornell University. Excerpt "The continuous downscaling of transistors in integrated circuits following Moore’s law—doubling the number of transistors on a microchip about every 2 years—has been an extraordinary feat of engineering, pushing the limits of fu... » read more

HBM Leads The Way To Defect-Free Bumps
By Laura Peters - 11 Nov, 2025 - Comments: 0

High-bandwidth memory stands at the forefront of multiple technology developments as a critical enabler of AI, but it is one of the most difficult modules to manufacture. Leading HBM device makers and foundries must simultaneously handle multi-layer chip stacking, die warpage, and shorter product lifecycles that are shrinking from two years down to just one. But perhaps the most formidable c... » read more

Developing RISC-V Compute Subsystems
By Baya Systems - 29 Oct, 2025 - Comments: 0

As demand grows for scalable, efficient, and customized compute, more companies are turning to RISC-V as the preferred architecture for high-performance computing. Tenstorrent and Baya Systems have designed a compute subsystem combining IP from both companies designed to enable AI and HPC use cases. The solution leverages Tenstorrent’s Ascalon processor and Baya’s advanced interconnect tech... » read more

Interconnect Innovations In High Bandwidth Memory: Part 2
By Damon Tsai - 14 Oct, 2025 - Comments: 0

By Damon Tsai, Woo Young Han, and Tim Kryman Interconnect technology in high bandwidth memory (HBM) is at a fork in the road. One direction leads to tried-and-true microbump technology, and the other leads to a compelling alternative, hybrid bonding. Both technologies are evolving to address the stringent requirements of next generation HBM in pursuit of increased I/O density supporting high... » read more

A Modular System In Package Approach For Automotive Short Range Radar Applications (Ruhr Univ. Bochum, Fraunhofer et al.)
By Technical Paper Link - 03 Oct, 2025 - Comments: 0

A new technical paper titled “Leveraging Modularity of Chiplets to Form a 4×4 Automotive FMCW-Radar in an eWLB-Package” was published by researchers at Ruhr University Bochum, Fraunhofer Institute, University Bremen, Infineon and WavesenseDD GmbH. Abstract “Dividing a System on Chip (SoC) into multiple smaller chiplets and embedding them into a single package has gained significant t... » read more

The Future Of SoC Design Is Data Movement
By Andy Nightingale - 25 Sep, 2025 - Comments: 0

The semiconductor industry is experiencing rapid advances in chiplet adoption, high-bandwidth memory, Compute Express Link (CXL) fabrics, and automotive zonal architectures. As we move into the second half of 2025, the only sustainable path forward is a layered, physically aware, and automated interconnect methodology that can keep pace with escalating complexity. This article is Part Two of... » read more

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