tag: interconnects

Breaking The Copper Bottleneck With Molybdenum Hybrid Metallization
By Taeyeon Oh - 18 Sep, 2025 - Comments: 0

Scaling the back end of line (BEOL) in advanced semiconductor logic devices is a major challenge. Metal lines and via filling in BEOL have historically used copper (Cu) as the electrical conductor. But as device dimensions shrink, Cu use has become problematic. The small critical dimensions (CD) of the Cu metal lines and vias in the latest BEOL structures have created an increase in resistance,... » read more

Precision Under Pressure: Managing Materials Complexity In Advanced Packaging
By Gregory Haley - 18 Sep, 2025 - Comments: 0

In the race to extend Moore's Law through advanced packaging, the limits of precision are no longer defined solely by lithography. Increasingly, they are dictated by the unpredictable behavior of materials. Semiconductor packaging today is no longer limited to just silicon and copper. It includes an expanding range of polymers, adhesives, dielectrics, exotic metals, along with substrates suc... » read more

Scaling Memory With Molybdenum
By Katherine Derbyshire - 18 Sep, 2025 - Comments: 2

Molybdenum is looking increasingly promising as a replacement for a variety of metals commonly used in semiconductor manufacturing today, especially at leading-edge nodes. One by one, chipmakers are crossing metals off the list at advanced nodes. While ruthenium liners are nearly ready for production, the metal is not ready to replace copper in highly scaled interconnects. Ruthenium is very ... » read more

Interconnect Innovations In High Bandwidth Memory: Part 1
By Damon Tsai - 09 Sep, 2025 - Comments: 0

By Damon Tsai, Woo Young Han, and Tim Kryman The demand for high bandwidth memory (HBM) is accelerating across the semiconductor industry, driven by boundary-pushing artificial intelligence, high-performance computing, and advanced graphics. These technologies require access to vast datasets, which in turn increases the need for memory solutions that combine speed, density, and power efficie... » read more

Wafer-Scale Heterogeneous Integration of Lithium Tantalate Films on Low-Loss Silicon Nitride Photonic ICs (EPFL, KIT, CAS, IPQ)
By Technical Paper Link - 03 Sep, 2025 - Comments: 0

A new technical paper titled "Heterogeneously integrated lithium tantalate-on-silicon nitride modulators for high-speed communications" was published by researchers at EPFL, Chinese Academy of Sciences, IPQ and KIT. Abstract "Driven by the prospects of higher bandwidths for optical interconnects, integrated modulators involving materials beyond those available in silicon manufacturing incre... » read more

Chiplet Design Considerations
By Robert Kruger - 28 Aug, 2025 - Comments: 0

Chiplets are a way to offer continuing increases in compute capacity and I/O bandwidth needs by splitting SoC functionality into smaller heterogeneous or homogeneous dies called chiplets and integrating these chiplets into a single system in package (SIP), where the total silicon content can exceed the reticle size of a single SoC. SIP includes traditional package substrates but also may includ... » read more

Reticle Stitching Bumps Up Silicon Interposer Costs
By Bryon Moyer - 21 Aug, 2025 - Comments: 0

Advanced packaging often relies on silicon interposers to connect chiplets and other components inside a package. The problem is that interposers typically exceed the reticle limit, which adds both complexity and cost. An interposer is essential for 2.5D and 3.5D architectures. As device scaling runs out of steam, chipmakers are decomposing planar SoCs into chiplets and connecting them throu... » read more

The End Of Copper Interconnects?
By Katherine Derbyshire - 21 Aug, 2025 - Comments: 0

After nearly three decades, the era of copper interconnects may be coming to an end. Sort of. At interconnect CDs below 10nm, copper is no longer the best metallization choice. Yet it remains unsurpassed for larger features. The most serious challenge to continued copper scaling is the metal’s dramatic increase in resistivity at dimensions below its relatively large (40nm) mean free path l... » read more

Server-Scale Programmable Photonic Fabric to Interconnect Accelerators Within Servers (Cornell University, Lightmatter)
By Technical Paper Link - 15 Aug, 2025 - Comments: 0

A new technical paper titled "Morphlux: Programmable chip-to-chip photonic fabrics in multi-accelerator servers for ML" was published by researchers at Cornell University and Lightmatter. Abstract "We optically interconnect accelerator chips (e.g., GPUs, TPUs) within compute servers using newly viable programmable chip-to-chip photonic fabrics. In contrast, today, commercial multi-accelerat... » read more

System-Level Design For 1.6 Tbps Interoperability In AI Data Centers
By Madhumita Sanyal - 14 Aug, 2025 - Comments: 0

By Madhumita Sanyal and Diwakar Kumaraswamy The rapid escalation of AI/ML workloads—driven by increasingly large language models—is reshaping high-performance computing and AI data center architectures. Real-time inference and large-scale training are pushing the limits of compute and interconnect performance. With model sizes and parameter counts doubling every 4–6 months, infrastruct... » read more

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