tag: interconnects

Low-Latency Interconnect for Close-Coupled On-Chip Communication With Error Correction Code Protection (ETH Zurich)
By Technical Paper Link - 11 Aug, 2025 - Comments: 0

A new technical paper titled "relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication" was published by researchers at ETH Zurich. Excerpt "On-chip communication is a critical element of modern systems-on-chip (SoCs), allowing processor cores to interact with memory and peripherals. Interconnects require special care in radiation-heavy environments, as any soft... » read more

On-Die And In-Package Interconnects: eBook
By Bryon Moyer - 28 Jul, 2025 - Comments: 0

We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

Using Picosecond Ultrasonic Technology For AI Packages: Part 2
By Cheolkyu Kim - 10 Jul, 2025 - Comments: 0

Heterogeneous integration is a key enabler of today’s AI innovations. By bringing together multiple chips with different functionalities, a.k.a., chiplets, AI devices have been able to achieve tremendous performance gains. However, the heterogeneous integration of advanced packages has its own set of process control obstacles that must be addressed, including new interconnect challenges invol... » read more

EDA’s Top Execs Map Out An AI-Driven Future
By Ed Sperling - 23 Jun, 2025 - Comments: 0

Artificial intelligence is permeating the entire semiconductor ecosystem, forcing fundamental changes in AI chips, the design tools used to create them, and the methodologies used to ensure they will work reliably. This is a global race that will redefine nearly every domain over the next decade. In presentations and interviews over the past several months, top EDA executives converged on th... » read more

Front-End Technologies Are The New Back-End Tools: Using Picosecond Ultrasonics Technology For AI Packages, Part 1
By Cheolkyu Kim - 10 Jun, 2025 - Comments: 0

If you are a part of the semiconductor industry or simply someone interested in the field, you have likely heard what has become a common refrain: the back-end of the process is becoming more like the front-end of the process. In other words, the technologies that were once exclusively deployed in the first part of the process are being used to meet the increasingly stringent requirements of ad... » read more

Accelerating Scalable Computing
By Shivi Arora - 02 Jun, 2025 - Comments: 0

By Shivi Arora and Sue Hung Fung As computing demands for HPC, AI/ML, and cloud infrastructure grow, modular architectures are replacing traditional monolithic System-on-Chip (SoC) designs. These legacy designs are increasingly expensive and difficult to scale due to ever-increasing silicon complexity. In response, the industry is embracing chiplet-based System-in-Package (SiP) solutions,... » read more

Molybdenum: Transforming Semiconductor Manufacturing For Next-Generation Technologies
By Lam Research - 22 May, 2025 - Comments: 0

One trillion semiconductors produced in a single year. A digital foundation powering AI's explosive growth. The next frontier requires chips that are smaller, faster, and exponentially more powerful. A new white paper from Counterpoint Research  reveals how advanced metallization—specifically molybdenum—is becoming a critical enabler for semiconductor manufacturing in this new era. Th... » read more

More Data, More Redundant Interconnects
By Ed Sperling - 19 May, 2025 - Comments: 0

The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

Demonstration Of EUV Scatterometry On A 2D Periodic Interconnect
By Technical Paper Link - 18 May, 2025 - Comments: 0

A new technical paper titled "Coherent EUV scatterometry of 2D periodic structure profiles with mathematically optimal experimental design" was published by researchers at University of Colorado, NIST, Samsung and KMLAbs. Abstract "Extreme ultraviolet (EUV) scatterometry is an increasingly important metrology that can measure critical parameters of periodic nanostructured materials in a fas... » read more

Die-to-die Interconnect Standards In Flux
By Bryon Moyer - 15 May, 2025 - Comments: 0

UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. ... » read more

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