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Low-Latency Interconnect for Close-Coupled On-Chip Communication With Error Correction Code Protection (ETH Zurich)

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A new technical paper titled “relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication” was published by researchers at ETH Zurich.

Excerpt
“On-chip communication is a critical element of modern systems-on-chip (SoCs), allowing processor cores to interact with memory and peripherals. Interconnects require special care in radiation-heavy environments, as any soft error within the SoC interconnect is likely to cause a functional failure of the whole SoC. This work proposes relOBI, an extension to Open Bus Interface (OBI) combining triple modular redundancy (TMR) for critical handshake signals with error correction codes (ECC) protection on other signals for complete reliability. Implementing and testing a fully reliable crossbar shows improved reliability to injected faults from a vulnerability of 34.85 % to 0 % compared to a reference design, with an area increase of 2.6x and 1.4x timing impact. The area overhead is 1.8x lower than that reported in the literature for fine-grained triplication and voting.”

Find the technical paper here. August 2025.

Rogenmoser, Michael, Angelo Garofalo, and Luca Benini. “relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication.” arXiv preprint arXiv:2508.05354 (2025).


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