Cost-Effective, Orthogonal Approach to Resilient Memory Design (Univ. of Central Florida, UT San Antonio, Rochester)


A new technical paper titled "SCREME: A Scalable Framework for Resilient Memory Design" was published by researchers at University of Central Florida, University of Texas at San Antonio and University of Rochester. Abstract "The continuing advancement of memory technology has not only fueled a surge in performance, but also substantially exacerbate reliability challenges. Traditional soluti... » read more

Low-Latency Interconnect for Close-Coupled On-Chip Communication With Error Correction Code Protection (ETH Zurich)


A new technical paper titled "relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication" was published by researchers at ETH Zurich. Excerpt "On-chip communication is a critical element of modern systems-on-chip (SoCs), allowing processor cores to interact with memory and peripherals. Interconnects require special care in radiation-heavy environments, as any soft... » read more

Power/Performance Bits: Nov. 30


Universal decoding algorithm Researchers at MIT, Boston University, and Maynooth University built a silicon chip that is able to decode any error-correcting code, regardless of its structure, with maximum accuracy, using a universal decoding algorithm called Guessing Random Additive Noise Decoding (GRAND). Encoded data traveling over a network is susceptible to noise, which disrupts the sig... » read more