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Intelligent Waveform Replay For Efficient Debug


There is no doubt that design reuse is essential for today’s massive system on chip (SoC) projects. No team, no matter how large or how talented, can design billions of gates from scratch for each new chip. From the earliest days, development teams have leveraged existing gate level designs and register transfer level (RTL) code whenever possible. The emergence of the commercial intellectual ... » read more

Four Requirements To Improve Chip Design Debug


Debug has always been a painful and unavoidable part of semiconductor design and, despite many technological advances, it remains one of the dominant tasks in chip development. At one time, most bugs were detected and diagnosed on actual devices in the bring-up lab, where both visibility and controllability are severely limited. It is certainly true that debugging the results from pre-silicon t... » read more

Early Simulation Of Multi-Cycle Paths And False Paths


Designing with synchronous clocks avoids metastability issues on clock domain crossings, but it presents its own challenges when multi-cycle and false paths are involved. A multi-cycle path (MCP) occurs when a logical function requires more than one clock cycle to produce a final, stable result. The designer must ensure that the destination register does not clock until the result is ready. Thi... » read more

Know Your Own Power, Early And Accurately


By Taruna Reddy and Vin Liao Chip designers have always had to balance timing and area. Everyone wants a design as fast as possible and as compact as possible, but these two goals are usually in conflict. For the last couple of decades, minimal power consumption has been a third goal, often of equal importance. Some of the biggest drivers for the semiconductor industry are battery operated p... » read more

Simulation: Go Parallel Or Go Home


Although complemented by other valuable technologies, functional simulation remains at the heart of semiconductor verification. Every chip project still develops a testbench, usually compliant with the Universal Verification Methodology (UVM), and a large test suite. Constrained-random stimulus generation has largely replaced hand-crafted tests, but at the expense of much more simulation time. ... » read more