Taruna Reddy

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Taruna Reddy is a senior product marketing manager in the Verification Group at Synopsys. Reddy has 14 years of experience in EDA and functional verification. Prior to joining Synopsys, she held field applications and verification engineering positions at Mentor Graphics, Verilab and Xtreme-EDA. She holds a MSEE from Clemson University and Bachelor of Technology from India.

Author's Latest Posts

Verifying Hardware Security With RTL Simulation
By Taruna Reddy - 14 Mar, 2024 - Comments: 0

When consumers think about security for their electronic gadgets, financial applications probably spring first to mind. Identity theft and unauthorized access to bank and investment accounts are a constant threat. But there’s more to worry about every day. Stories of webcams and smart speakers being hacked are all over the web. Users rightfully demand that device manufacturers provide a high ... » read more

New Technology Accelerates Multi-Die System Simulation
By Taruna Reddy - 27 Jul, 2023 - Comments: 0

AI-powered chatbots. Robotic manufacturing equipment. Self-driving cars. Bandwidth-intensive applications like these are flourishing—and driving the move from monolithic system-on-chips (SoCs) to multi-die systems. By integrating multiple dies, or chiplets, into a single package, designers can achieve scaling of system functionality at reduced risk and with faster time to market. Multi-die... » read more

How AI Drives Faster Verification Coverage And Debug For First-Time-Right Silicon
By Taruna Reddy - 23 Mar, 2023 - Comments: 0

By Taruna Reddy and Robert Ruiz These days, the question is less about what AI can do and more about what it can’t do. From talk-of-the-town chatbots like ChatGPT to self-driving cars, AI is becoming pervasive in our everyday lives. Even industries where it was perhaps an unlikely fit, like chip design, are benefiting from greater intelligence. What if one of the most laborious, time-co... » read more

Intelligent Waveform Replay For Efficient Debug
By Taruna Reddy - 24 Feb, 2022 - Comments: 0

There is no doubt that design reuse is essential for today’s massive system on chip (SoC) projects. No team, no matter how large or how talented, can design billions of gates from scratch for each new chip. From the earliest days, development teams have leveraged existing gate level designs and register transfer level (RTL) code whenever possible. The emergence of the commercial intellectual ... » read more

Four Requirements To Improve Chip Design Debug
By Taruna Reddy - 26 Aug, 2021 - Comments: 0

Debug has always been a painful and unavoidable part of semiconductor design and, despite many technological advances, it remains one of the dominant tasks in chip development. At one time, most bugs were detected and diagnosed on actual devices in the bring-up lab, where both visibility and controllability are severely limited. It is certainly true that debugging the results from pre-silicon t... » read more

Early Simulation Of Multi-Cycle Paths And False Paths
By Taruna Reddy - 24 Jun, 2021 - Comments: 0

Designing with synchronous clocks avoids metastability issues on clock domain crossings, but it presents its own challenges when multi-cycle and false paths are involved. A multi-cycle path (MCP) occurs when a logical function requires more than one clock cycle to produce a final, stable result. The designer must ensure that the destination register does not clock until the result is ready. Thi... » read more

Know Your Own Power, Early And Accurately
By Taruna Reddy - 11 Feb, 2021 - Comments: 0

By Taruna Reddy and Vin Liao Chip designers have always had to balance timing and area. Everyone wants a design as fast as possible and as compact as possible, but these two goals are usually in conflict. For the last couple of decades, minimal power consumption has been a third goal, often of equal importance. Some of the biggest drivers for the semiconductor industry are battery operated p... » read more

Simulation: Go Parallel Or Go Home
By Taruna Reddy - 27 Feb, 2020 - Comments: 0

Although complemented by other valuable technologies, functional simulation remains at the heart of semiconductor verification. Every chip project still develops a testbench, usually compliant with the Universal Verification Methodology (UVM), and a large test suite. Constrained-random stimulus generation has largely replaced hand-crafted tests, but at the expense of much more simulation time. ... » read more

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