Know Your Own Power, Early And Accurately

A power estimation method that occurs earlier in the development cycle with nearly the same accuracy.


By Taruna Reddy and Vin Liao

Chip designers have always had to balance timing and area. Everyone wants a design as fast as possible and as compact as possible, but these two goals are usually in conflict. For the last couple of decades, minimal power consumption has been a third goal, often of equal importance. Some of the biggest drivers for the semiconductor industry are battery operated products such as smartphones, tablets, and Internet of Things (IoT) devices. Time between recharges or battery replacements is often an important product feature. Even for wall powered applications such as compute servers and networking infrastructure, the total energy consumed is a key factor in lifetime cost of ownership.

This focus on power ripples down to every aspect of design and verification of modern system on chip (SoC) devices. Architects address power saving techniques from the initial specification, designers implement these techniques, layout engineers create special circuits and the verification team ensures that everything works together to keep power consumption within the specified limits. The design team must be able to estimate power during the development process so that any issues can be addressed before fabrication. Finding that an SoC consumes too much power in the bring-up lab is way too late. Pre-silicon power estimation must be fast enough to perform repeatedly throughout the project and accurate enough to avoid unpleasant surprises in the lab.

Fortunately, there is a widely accepted method for highly accurate power consumption analysis that correlates closely to measurements from fabricated chips. This entails running gate-level simulation (GLS) with full timing information back-annotated onto the post-synthesis or post-place-and-route netlist. Most power is consumed when gates switch, so the detailed timing data is critical to determine when switching occurs. The more switching activity in parallel, the higher the peak power consumption. The GLS approach is used for power signoff precisely because it is so accurate. However, there are major limitations on using this as the only power estimation technique:

  • GLS occurs very late in the project, after the entire design has been completed, verified and synthesized, when fixing power issues may cause a schedule slip
  • GLS requires significant engineering effort to set up and run
  • GLS is much slower than register transfer level (RTL) simulation, so only a subset of the test suite can be run, possibly reducing estimation accuracy

One partial solution is running power analysis based on RTL simulation to “shift left” the results. Simulators produce switching activity files that can be used to estimate power consumption early in the development process. The results are accurate enough to highlight major power issues at a project stage when it is easy to fix them without compromising the schedule. However, there is a limit to how accurate this analysis can be since the detailed timing files are not yet available, and timing varies widely depending upon the selected synthesis options and the resulting netlist. Despite the value of power estimation based on RTL simulation, there is still a chance that GLS with full timing will turn up problems that are hard to address late in the project.

Designers need a power estimation method that occurs earlier in the development cycle than GLS with nearly the same level of accuracy. The Synopsys PowerReplay solution has been proven on many SoC projects to meet these requirements. It performs early and fast gate-level power analysis at an accuracy within 5% of power signoff.

PowerReplay uses the results from RTL simulation and runs netlist simulation internally without users having to port the RTL testbench to GLS or perform any of the setup required for power signoff. PowerReplay reads in the RTL design, the RTL simulation results in the form of a fast signal database (FSDB) trace file and the gate-level netlist. The first step is performing a mapping from gates to RTL, optionally aided by a Setup Verification for Formality (SVF) file from logic synthesis. The second step is running GLS using RTL simulation results and the gate-level netlist. PowerReplay automatically generates a gate-level testbench that can apply the GLS inputs using the RTL FSDB values and check the GLS outputs against the RTL FSDB values.

This process works for any portion of the design, so it can be run on individual blocks or subsystems long before the entire chip is ready to be synthesized. Users can choose a subset of the design or a subset of the simulation trace, for example deferring power analysis until after configuration is complete.

A white paper is available with detailed information on advanced features, and more.

Power is every bit as important as area and timing in the planning and development of SoC designs. Successful end products must operate within their power budgets, and any issues must be found well before the bring-up lab. Design engineers must have timely, accurate power estimation results throughout the development schedule.

Vin Liao is a Staff Application Engineer in the Verification Group at Synopsys. Liao has been working in EDA industry for more than a decade and is experienced in debug and functional verification. Prior to joining Synopsys, Liao held research and developer at SpringSoft acquired by Synopsys. He holds a MSEE from National Tsing Hua University and a Bachelor of EE from National Chao Tung University from Taiwan.

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