tag: PPA

Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design
By Synopsys - 11 Jun, 2026 - Comments: 0

Access “Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design” to explore six articles that explain how to address SoC design challenges using advanced Foundation IP solutions. Learn how these approaches enable energy efficiency, high performance, and reliability across key applications such as mobile, IoT, AI, HPC, automotive, crypto, and networking. Why read this digest... » read more

Beating the Edge AI Power Wall with Low Voltage Foundation IP
By Synopsys - 03 Jun, 2026 - Comments: 0

Edge AI is pushing the limits of power efficiency as intelligence moves closer to the data source. Designing for ultra-low voltage operation is now essential to achieve optimal performance-per-watt—but it introduces significant complexity in modeling, variation, and design predictability. In this white paper, discover how a unified, silicon-proven Foundation IP platform approach enables relia... » read more

Supporting Safety Requirements from RTL Exploration Through Implementation in Semiconductor Devices (Politecnico di Torino, Synopsys)
By Technical Paper Link - 12 May, 2026 - Comments: 0

A new technical paper, "Early Functional Safety and PPA evaluation for faster digital design development," was published by researchers at Politecnico di Torino and Synopsys. Abstract "The use of semiconductor devices in safety-critical applications is increasing in both volume and complexity. Applications in markets such as automotive, data centers, and aerospace have dependability requi... » read more

Power, Not Area: Why Edge GPU Design Is Entering A New Era
By Ed Plowman - 05 Mar, 2026 - Comments: 0

For decades, semiconductor progress followed a familiar playbook: shrink the node, pack in more logic, raise the clock, and performance would follow. That model held remarkably well, and possibly much longer than it should have. As the industry moves below 2nm, GPU design is running into a hard physical reality. The limiting factor is no longer how much logic we can fit on a die. It’s how ... » read more

Power Leadership At 2nm: Foundation IP Optimized For Next-Gen Hyperscale SoCs
By Andrew Appleby - 12 Feb, 2026 - Comments: 0

By Andrew Appleby and Daryl Seitzer As demand for data center compute accelerates, power efficiency has become the defining metric for modern CPUs, GPUs, and AI accelerators. Every watt saved directly impacts the massive operating costs of gigawatt-scale AI data centers, where power and cooling account for 40–60% of operational expenditures. To reduce energy consumption and strengthen t... » read more

Why Move To 2nm?
By Ed Sperling - 04 Feb, 2026 - Comments: 0

Key Takeaways: Scaling digital logic still provides significant benefits, especially lower power. Multi-die assemblies will be the predominant approach, and most of the circuitry will not be 2nm or below. While these systems are inherently more flexible, the number and complexity of tradeoffs required for optimizing PPA/C are increasing. The rollout of 2nm process nodes and ... » read more

Co-optimization Approaches For Reliable and Efficient AI Acceleration (Peking University et al.)
By Technical Paper Link - 21 Jan, 2026 - Comments: 0

A new technical paper titled "The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization" was published by researchers at Peking University and Beijing Advanced Innovation Center for Integrated Circuits. Abstract "As the CMOS technology pushes to the nanoscale, aging effects and process variations have become increasingly pronounced, posing significant reliabilit... » read more

How And Why To Optimize NPUs
By Ann Mutschler - 15 Jan, 2026 - Comments: 0

Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones.  Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven... » read more

Limited by Power
By Brian Bailey - 11 Dec, 2025 - Comments: 0

AI is seen as a massive computation problem, but that is not the case, at least with the way that the problem is structured today. It is a data movement problem. This not only limits performance but represents most of the energy consumption. In addition, the industry spends most of its time and effort making small improvements that optimize aspects of the existing architecture, when what is ... » read more

Adding Cost, Cycle Time, And Carbon Footprint To PPA Design Targets
By Shela Aboud - 20 Nov, 2025 - Comments: 0

When engineers start designing a new semiconductor technology and fabrication process, they set targets to define what they are trying to achieve to meet the market demands and beat competitive offerings. Traditionally, they have used the metrics of power, performance, and area (PPA). This post examines how additional design targets are mandated by today’s deep submicron nodes and how develop... » read more

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