tag: PPA

Getting Optimal PPA For HPC & AI Applications With Foundation IP
By Andrew Appleby - 11 Jan, 2024 - Comments: 0

By Andrew Appleby, Xiaorui Hu, and Bhavana Chaurasia The demand for application-specific system-on-chips (SoCs) for compute applications is ever-increasing. Today, the diversity of requirements means there is a need for a rich set of compute solutions in a wide range of process technologies. The resulting products may have very different but demanding power, performance, and area (PPA) requi... » read more

AI-Driven Macro Placement Boosts PPA
By Janet Attar - 11 Jan, 2024 - Comments: 0

In the era of EDA 4.0, artificial intelligence (AI) and machine learning (ML) are transforming what electronic design automation tools are capable of. For many of the challenges of physical IC design, AI can provide significant benefits to both the turnaround time and the quality of the design, as measured by performance, power, and area (PPA) metrics. One implementation step due for improve... » read more

Achieving High-Performance, Low-Power Design Optimization With The Solido Library IP Solution
By Siemens EDA - 13 Dec, 2023 - Comments: 0

Achieving overall power, performance, and area (PPA) targets is a key goal for today’s advanced IC design projects. To accomplish this, standard cell and memory libraries must be optimized for PPA. In this white paper, we describe how the Siemens Solido IP Library Solution helps engineering teams design and verify library IP to optimize PPA tradeoffs, maximize yield, and validate for easy int... » read more

Flipping Processor Design On Its Head
By Ann Mutschler - 09 Nov, 2023 - Comments: 2

AI is changing processor design in fundamental ways, combining customized processing elements for specific AI workloads with more traditional processors for other tasks. But the tradeoffs are increasingly confusing, complex, and challenging to manage. For example, workloads can change faster than the time it takes to churn out customized designs. In addition, the AI-specific processes may ex... » read more

Performance & Efficiency Cores For Servers
By Barry Pangrle - 31 Aug, 2023 - Comments: 0

HotChips 2023 was held August 27-29, 2023 at Stanford University in California and was the first in-person version of the conference in 4 years. The conference was held in a hybrid format that had over 500 participants in-person and over 1,000 attending virtually online. Topics covered a broad range of advancements in computing, connectivity, and computer architecture. Both AMD and Intel gav... » read more

Challenges In Ramping New Manufacturing Processes
By Ed Sperling - 30 Aug, 2023 - Comments: 0

Despite a slowdown for Moore’s Law, there are more new manufacturing processes rolling out faster than ever before. The challenge now is to decrease time to yield, which involves everything from TCAD and design technology co-optimization, to refinement of power, performance, area/cost, and process control and analytics. Srinivas Raghvendra, vice president of engineering at Synopsys, talks abo... » read more

Developing Energy-Efficient AI Accelerators For Intelligent Edge Computing And Data Centers
By William Ruby - 10 Aug, 2023 - Comments: 0

Artificial intelligence (AI) accelerators are deployed in data centers and at the edge to overcome conventional von Neumann bottlenecks by rapidly processing petabytes of information. Even as Moore’s law slows, AI accelerators continue to efficiently enable key applications that many of us increasingly rely on, from ChatGPT and advanced driver assistance systems (ADAS) to smart edge device... » read more

Battling Over Shrinking Physical Margin In Chips
By Ed Sperling - 31 Jul, 2023 - Comments: 0

Smaller process nodes, coupled with a continual quest to add more features into designs, are forcing chipmakers and systems companies to choose which design and manufacturing groups have access to a shrinking pool of technology margin. In the past margin largely was split between the foundries, which imposed highly restrictive design rules (RDRs) to compensate for uncertainties in new proces... » read more

The Impact Of ML On Chip Design
By Ed Sperling - 22 May, 2023 - Comments: 0

Node scaling and rising complexity are increasing the time it takes to get chips out the door. At the same time, design teams are not getting larger. What is needed is a way to automate the creative process, and to not have to start every design from scratch. This is where reinforcement learning fits in, with its ability to centralize and store “tribal knowledge. Thomas Andersen, vice preside... » read more

Combination of AI Techniques To Find The Best Ways to Place Transistors on Silicon Chips
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "AutoDMP: Automated DREAMPlace-based Macro Placement" was published by researchers at NVIDIA. Abstract: "Macro placement is a critical very large-scale integration (VLSI) physical design problem that significantly impacts the design power-performance-area (PPA) metrics. This paper proposes AutoDMP, a methodology that leverages DREAMPlace, a GPU-accelerated place... » read more

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