tag: PPA

Realizing The Future Of 3D-IC: Final Scenario And Sign-off
By Keith Felton - 23 Jul, 2026 - Comments: 0

By Keith Felton and Todd Burkholder Multi-chiplet packages contain thousands of connections between chiplets, interposers, and package BGAs. After optimizing this complex connectivity, designers must identify related signal groups (interfaces or buses) and plan their path from the chiplet bump field to target bumps or BGA balls. This involves managing multiple groups, considering available r... » read more

An AI Model Fit For Purpose
By Brian Bailey - 09 Jul, 2026 - Comments: 0

Key takeaways A model can only be used for its intended purpose, in a defined context, without taking unknown risks. Models must be created using a well-defined process and verified in a way that provides a level of independence. Deployment requires trust and a way to track the properties of the model. A model captures some kind of behavior exhibited in the real world, but a... » read more

How Far Left Can We Really Shift Verification?
By Frank Schirrmeister - 25 Jun, 2026 - Comments: 0

"Shift left" has been in the engineering lexicon for so long that it risks becoming wallpaper. We nod at it, we put it on slides, and we move on. But the goalposts keep moving. Things that used to live comfortably at the tail end of the design flow — software bring-up, power and performance characterization, thermal analysis — are being dragged earlier and earlier into the schedule, driven ... » read more

Realizing The Future Of 3D-IC Design
By Keith Felton - 25 Jun, 2026 - Comments: 0

The integration of heterogeneous chiplet technology has fundamentally transformed semiconductor design, enabling the efficient creation of sophisticated system-in-packages by assembling pre-designed or third-party IP onto high-performance interposers and advanced packages. This approach offers significant advantages over traditional monolithic designs, including enhanced performance, improved p... » read more

Signoff Of Synthesis-Optimized Registers
By Ed Sperling - 17 Jun, 2026 - Comments: 0

How do you know when you sign off on a complex chip design that everything is going to work? There are more variables, more elements that need to be verified, and more waivers that need to be generated. Suresh Barla, senior director of field applications at Synopsys, talks about how to ensure that RTL is fully optimized for PPA targets in large designs that can include hundreds of millions of g... » read more

Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design
By Synopsys - 11 Jun, 2026 - Comments: 0

Access “Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design” to explore six articles that explain how to address SoC design challenges using advanced Foundation IP solutions. Learn how these approaches enable energy efficiency, high performance, and reliability across key applications such as mobile, IoT, AI, HPC, automotive, crypto, and networking. Why read this digest... » read more

Beating the Edge AI Power Wall with Low Voltage Foundation IP
By Synopsys - 03 Jun, 2026 - Comments: 0

Edge AI is pushing the limits of power efficiency as intelligence moves closer to the data source. Designing for ultra-low voltage operation is now essential to achieve optimal performance-per-watt—but it introduces significant complexity in modeling, variation, and design predictability. In this white paper, discover how a unified, silicon-proven Foundation IP platform approach enables relia... » read more

Supporting Safety Requirements from RTL Exploration Through Implementation in Semiconductor Devices (Politecnico di Torino, Synopsys)
By Technical Paper Link - 12 May, 2026 - Comments: 0

A new technical paper, "Early Functional Safety and PPA evaluation for faster digital design development," was published by researchers at Politecnico di Torino and Synopsys. Abstract "The use of semiconductor devices in safety-critical applications is increasing in both volume and complexity. Applications in markets such as automotive, data centers, and aerospace have dependability requi... » read more

Power, Not Area: Why Edge GPU Design Is Entering A New Era
By Ed Plowman - 05 Mar, 2026 - Comments: 0

For decades, semiconductor progress followed a familiar playbook: shrink the node, pack in more logic, raise the clock, and performance would follow. That model held remarkably well, and possibly much longer than it should have. As the industry moves below 2nm, GPU design is running into a hard physical reality. The limiting factor is no longer how much logic we can fit on a die. It’s how ... » read more

Power Leadership At 2nm: Foundation IP Optimized For Next-Gen Hyperscale SoCs
By Andrew Appleby - 12 Feb, 2026 - Comments: 0

By Andrew Appleby and Daryl Seitzer As demand for data center compute accelerates, power efficiency has become the defining metric for modern CPUs, GPUs, and AI accelerators. Every watt saved directly impacts the massive operating costs of gigawatt-scale AI data centers, where power and cooling account for 40–60% of operational expenditures. To reduce energy consumption and strengthen t... » read more

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