The Fast, ‘Attractive’ Path From Great PPA To The Best PPA For High-Performance Arm Cores


By Mark Richards and Neel Desai When you want to create a website for your new side-hustle, or maybe for your local soccer team, it's rare that you would order a book on cascading-style sheets, break out the HTML editor and start from a blank sheet of “paper.” You'd do the smart thing and use a website builder, link it to some content management tool (this would get you to 90% of a usabl... » read more

Best Full-Flow PPA


In the past few years, Cadence revolutionized the way digital designers could solve their design challenges by revamping the entire digital tool suite with key enhancements such as integrated engines, massively parallel processing, and early signoff optimization, all delivering faster turnaround time and best-in-class power, performance, and area (PPA) optimization. In the era of FinFETs and ad... » read more

Why It’s So Hard To Create New Processors


The introduction, and initial success, of the RISC-V processor ISA has reignited interest in the design of custom processors, but the industry is now grappling with how to verify them. The expertise and tools that were once in the market have been consolidated into the hands of the few companies that have been shipping processor chips or IP cores over the past 20 years. Verification of a pro... » read more

Automotive Chip Design Workflow


Stewart Williams, senior technical marketing manager at Synopsys, talks about the consolidation of chips in a vehicle and the impact of 7/5nm on automotive SoC design, how to trade off power, performance, area and reliability, and how ISO 26262 impacts those variables. » read more

Non-Volatile Memory Tradeoffs Intensify


Non-volatile memory is becoming more complicated at advanced nodes, where price, speed, power and utilization are feeding into some very application-specific tradeoffs about where to place that memory. NVM can be embedded into a chip, or it can be moved off chip with various types of interconnect technology. But that decision is more complicated than it might first appear. It depends on the ... » read more

Optimizing Power And Performance For Machine Learning At The Edge


While machine learning (ML) algorithms are popular for running on enterprise Cloud systems for training neural networks, AI/ML chipsets for edge devices are growing at a triple digit rate, according to Tractica “Deep Learning Chipsets” (Figure 1). Edge devices include automobiles, drones, and mobile devices that are all employing AI/ML to provide valuable functionality. Figure 1: Marke... » read more

Rapid Evolution For Verification Plans


Verification plans are rapidly evolving from mechanisms to track verification progress into multi-faceted coordination vehicles for several teams with disparate goals, using complex resource management spread across multiple abstractions and tools. New system demands from industries such as automotive are forcing tighter integration of those plans with requirements management and product lif... » read more

Disaggregation Of The SoC


The rise of edge computing could do to the cloud what the PC did to the minicomputer and the mainframe. In the end, all of those co-existed (despite the fact that the minicomputer morphed into commodity servers from companies like Dell and HP). What's different this time around is that the computing done inside of those boxes is moving. It is being distributed in ways never considered feasi... » read more

Multiphysics Simulations for AI Silicon to System Success


Achieving power efficiency, power integrity, signal integrity, thermal integrity and reliability is paramount for enabling product success by overcoming the challenges of size and complexity in AI hardware and optimizing the same for rapidly evolving AI software. ANSYS’ comprehensive chip, package and system solutions empower AI hardware designers by breaking down design margins and siloed de... » read more

In-Chip Monitoring Becoming Essential Below 10nm


Rising systemic complexity and more potential interactions in heterogeneous designs is making it much more difficult to ensure a chip, or even a block within a chip, will functioning properly without actually monitoring that behavior in real-time. Continuous and sporadic monitoring have been creeping into designs for the past couple of decades. But it hasn’t always been clear how effective... » read more

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