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Aprisa Place-And-Route For Low-Power SoCs


The Aprisa digital design software helps designers address the many challenges of low-power designs. Aprisa is the most flexible IC place-and-route tool on the market—it accepts all industry-standard power formats, has excellent correlation to third-party signoff tools, and is easy to install, set up, and use. With effective technology and impressive usability, the Aprisa software ensures cos... » read more

PPA(V): Performance-Per-Watt Optimization With Variable Operating Voltage


Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform, uniquely built on a singular RTL... » read more

HBM3: Big Impact On Chip Design


An insatiable demand for bandwidth in everything from high-performance computing to AI training, gaming, and automotive applications is fueling the development of the next generation of high-bandwidth memory. HBM3 will bring a 2X bump in bandwidth and capacity per stack, as well as some other benefits. What was once considered a "slow and wide" memory technology to reduce signal traffic dela... » read more

3D IC: Opportunities, Challenges, And Solutions


Nearly every big city reaches a point in its evolution when it runs out of open space and starts building vertically. This enables far more apartments, offices and people per square mile, while avoiding the increased infrastructure costs of suburban sprawl. Semiconductors are evolving in much the same way. Moore’s Law is slowing, and adoption of new advanced technology nodes is slowing as wel... » read more

Hyper-Convergence Is The New Normal For Digital Implementation


The era of smart-everything has led to a surge in the need for semiconductor devices across a myriad of traditional and novel applications. These applications demand high performance yet energy-efficient compute over blazing-fast networks to service trillions of edge devices that are constantly consuming and generating large amounts of data. This surge has invigorated system architects to innov... » read more

Tape Out On Time With Demand Signoff DRC In P&R


Physical characteristics of devices have become progressively more complex even as design companies pack more devices on each die. Combining these characteristics with ever more demanding chip power, performance, and area (PPA) goals not only result in increased resource utilization but also challenge existing tools/flows/techniques. Adding on-demand signoff-quality DRC verification inside P&R ... » read more

Best 112G SerDes IP Architecture


Real world operation of a serializer/deserializer (SerDes) in a hyperscale data center is very demanding and requires robust performance in challenging conditions such as multitude of channel insertion loss, extreme temperature cycles, different types of packages with different trace lengths and discontinuities, etc. Hence, meeting interference tolerance (ITOL) and jitter tolerance (JTOL) compl... » read more

Cell Library Verification Using Symbolic Simulation


Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models describing the cell functionality, schematic derived transistor level netlists, place and route views, physical layout views, post-layout extracted netlists as well as characterized timing and power m... » read more

IP Solutions For A Data-Centric World


We’re in an era of sizeable growth in data and compute demand, along with increasing global data traffic. As a result, high-performance computing, data communications, networking, and storage systems are taking center stage in many application areas, driven by newer applications such as analytics, artificial intelligence (AI), genomics, and simulation-intensive workloads. Power efficiency, hi... » read more

AI Testing: Pushing Beyond DFT Architectures


Every day, more applications are deploying artificial intelligence (AI) system to increase automation beyond traditional systems. The continuous growth in computing demands of AI systems require designers to develop massive, highly parallel AI processor chips. Their large sizes and types of applications have a significant impact on their design and test methodologies. With thousands of repeated... » read more

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