tag: PPA

Adding Cost, Cycle Time, And Carbon Footprint To PPA Design Targets
By Shela Aboud - 20 Nov, 2025 - Comments: 0

When engineers start designing a new semiconductor technology and fabrication process, they set targets to define what they are trying to achieve to meet the market demands and beat competitive offerings. Traditionally, they have used the metrics of power, performance, and area (PPA). This post examines how additional design targets are mandated by today’s deep submicron nodes and how develop... » read more

SOT-Based MRAM Design At 7nm (Georgia Tech, Intel)
By Technical Paper Link - 31 Oct, 2025 - Comments: 0

A new technical paper titled "Comprehensive device to system co-design for SOT-MRAM at the 7nm node" was published by researchers at Georgia Institute of Technology and Intel. Abstract "This work presents a comprehensive spin-orbit torque (SOT) based random access memory (MRAM) design at the 7nm technology node, spanning from device-level characteristics to system-level power performance ar... » read more

Critical Optimization Factors For GenAI Chipmakers
By Alex Burlak - 14 Oct, 2025 - Comments: 0

Today’s GenAI arms race is fought with novel chip architectures and packaging. Specialized hardware designs are proliferating in the form of GPUs, TPUs, NPUs, and more, all tuned for parallelism and matrix-heavy AI math. In this hyper-competitive landscape, chip vendors scramble to differentiate their products on multiple fronts. They promise some mix of better performance, efficiency, or ... » read more

Cross-Node Scaling Potential of SOT-MRAM for Last-Level Caches (imec)
By Technical Paper Link - 02 Sep, 2025 - Comments: 0

A new technical paper titled "SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study" was published by researchers at imec, Leuven, and 3001 Belgium. Abstract "This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate th... » read more

Machine Learning Tools Help Bridge Design-To-Manufacturing Gap
By Katherine Derbyshire - 24 Jul, 2025 - Comments: 0

More aggressive feature scaling and increasingly complex transistor structures are driving a steady increase in process complexity, increasing the risk that a specified pattern may not be manufacturable with an acceptable yield. A single layer now requires more process steps, and each of those entails more tunable parameters than ever before. To help manage design risk, foundries provide det... » read more

Can Today’s Processor Architectures Be More Efficient?
By Bryon Moyer - 17 Jul, 2025 - Comments: 3

For years, processors focused on performance, and that performance had little accountability to anything else. Performance still matters, but now it must be accountable to power. If small gains in performance result in disproportionate power gains, designers may need to discard such improvements in favor of more power-efficient ones. Although current architectures undergo a steady cadence of... » read more

Innovus+ Synthesis And Implementation System
By Cadence - 14 May, 2025 - Comments: 0

The Innovus+ platform incorporates Innovus synthesis and Innovus implementation capabilities, all integrated into one unified environment for outstanding ease of use and power, performance, and area (PPA) results. Innovus+ Synthesis can be used standalone to generate physically aware netlists ready for handoff to other design teams, such as ASIC partners, or the implementation flow can conti... » read more

How To Optimize Silicon Utilization To Improve PPA
By Ashish Darbari - 29 Apr, 2025 - Comments: 0

In the semiconductor industry, optimizing Power, Performance, and Area (PPA) is a key challenge for designers and architects. Balancing these three factors often involves making trade-offs. Improving one variable might lead to sacrificing others. For example, boosting performance may result in increased power consumption and a larger silicon area, or some power-reducing techniques might reduce ... » read more

Multi-Die Design Start Guide
By Synopsys - 23 Apr, 2025 - Comments: 0

If you are exploring a multi-die project and need guidelines on getting started, this white paper is for you. Any engineer on a semiconductor design project has read many articles about the power, performance, and area (PPA), functional scalability, and time-to-market advantages of multi-die designs using 2.5D and 3D technologies. The advantages are the main reason the adoption of multi-die des... » read more

Challenges In Managing Chiplet Resources
By Ann Mutschler - 27 Mar, 2025 - Comments: 0

Managing chiplet resources is emerging as a significant and multi-faceted challenge as chiplets expand beyond the proprietary designs of large chipmakers and interact with other elements in a package or system. Poor resource management in chiplets adds an entirely new dimension to the usual power, performance, and area tradeoffs. It can lead to performance bottlenecks, because as chiplets co... » read more

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