tag: PPA

Why Move To 2nm?
By Ed Sperling - 04 Feb, 2026 - Comments: 0

Key Takeaways: Scaling digital logic still provides significant benefits, especially lower power. Multi-die assemblies will be the predominant approach, and most of the circuitry will not be 2nm or below. While these systems are inherently more flexible, the number and complexity of tradeoffs required for optimizing PPA/C are increasing. The rollout of 2nm process nodes and ... » read more

Co-optimization Approaches For Reliable and Efficient AI Acceleration (Peking University et al.)
By Technical Paper Link - 21 Jan, 2026 - Comments: 0

A new technical paper titled "The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization" was published by researchers at Peking University and Beijing Advanced Innovation Center for Integrated Circuits. Abstract "As the CMOS technology pushes to the nanoscale, aging effects and process variations have become increasingly pronounced, posing significant reliabilit... » read more

How And Why To Optimize NPUs
By Ann Mutschler - 15 Jan, 2026 - Comments: 0

Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones.  Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven... » read more

Limited by Power
By Brian Bailey - 11 Dec, 2025 - Comments: 0

AI is seen as a massive computation problem, but that is not the case, at least with the way that the problem is structured today. It is a data movement problem. This not only limits performance but represents most of the energy consumption. In addition, the industry spends most of its time and effort making small improvements that optimize aspects of the existing architecture, when what is ... » read more

Adding Cost, Cycle Time, And Carbon Footprint To PPA Design Targets
By Shela Aboud - 20 Nov, 2025 - Comments: 0

When engineers start designing a new semiconductor technology and fabrication process, they set targets to define what they are trying to achieve to meet the market demands and beat competitive offerings. Traditionally, they have used the metrics of power, performance, and area (PPA). This post examines how additional design targets are mandated by today’s deep submicron nodes and how develop... » read more

SOT-Based MRAM Design At 7nm (Georgia Tech, Intel)
By Technical Paper Link - 31 Oct, 2025 - Comments: 0

A new technical paper titled "Comprehensive device to system co-design for SOT-MRAM at the 7nm node" was published by researchers at Georgia Institute of Technology and Intel. Abstract "This work presents a comprehensive spin-orbit torque (SOT) based random access memory (MRAM) design at the 7nm technology node, spanning from device-level characteristics to system-level power performance ar... » read more

Critical Optimization Factors For GenAI Chipmakers
By Alex Burlak - 14 Oct, 2025 - Comments: 0

Today’s GenAI arms race is fought with novel chip architectures and packaging. Specialized hardware designs are proliferating in the form of GPUs, TPUs, NPUs, and more, all tuned for parallelism and matrix-heavy AI math. In this hyper-competitive landscape, chip vendors scramble to differentiate their products on multiple fronts. They promise some mix of better performance, efficiency, or ... » read more

Cross-Node Scaling Potential of SOT-MRAM for Last-Level Caches (imec)
By Technical Paper Link - 02 Sep, 2025 - Comments: 0

A new technical paper titled "SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study" was published by researchers at imec, Leuven, and 3001 Belgium. Abstract "This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate th... » read more

Machine Learning Tools Help Bridge Design-To-Manufacturing Gap
By Katherine Derbyshire - 24 Jul, 2025 - Comments: 0

More aggressive feature scaling and increasingly complex transistor structures are driving a steady increase in process complexity, increasing the risk that a specified pattern may not be manufacturable with an acceptable yield. A single layer now requires more process steps, and each of those entails more tunable parameters than ever before. To help manage design risk, foundries provide det... » read more

Can Today’s Processor Architectures Be More Efficient?
By Bryon Moyer - 17 Jul, 2025 - Comments: 3

For years, processors focused on performance, and that performance had little accountability to anything else. Performance still matters, but now it must be accountable to power. If small gains in performance result in disproportionate power gains, designers may need to discard such improvements in favor of more power-efficient ones. Although current architectures undergo a steady cadence of... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy