AI-Driven Macro Placement Boosts PPA

Creating a high-quality floorplan in a fraction of the time.


In the era of EDA 4.0, artificial intelligence (AI) and machine learning (ML) are transforming what electronic design automation tools are capable of. For many of the challenges of physical IC design, AI can provide significant benefits to both the turnaround time and the quality of the design, as measured by performance, power, and area (PPA) metrics.

One implementation step due for improvement with AI is floorplanning. Traditionally, floorplanning and macro placement have been handcrafted by a few experts based on design experience, project knowledge from previous versions, and intuition. This method works fine for chips with only dozens of macros. However, modern SoC designs contain hundreds of macros and designers need a more efficient way to place these macros.

Most automatic macro placers on the market today provide some guidance to get designers started with their floorplan but fall short of a full solution and end up limiting PPA gains. There are even a couple of AI packages for macro placement that attempt to improve this very tedious task, but they cannot yet provide the quality of results (QoR) that designers need to achieve, particularly for high-performance and low-power ICs.

Physical designers want an automatic macro placer

Floorplan quality, and especially macro placement, has increasingly become a critical challenge to achieving better physical design PPA and a faster total turnaround time. This is due to several factors (figure 1):

  1. The physical-aware RTL synthesis tools need to extract physical information based on macro placement and a rough standard cell placement, to provide accurate estimations for place and route.
  2. Downstream, the QoR achieved by the place and route flow is highly sensitive to macro placement. A bad floorplan will lead to painful iterations and much longer total turnaround time.

Fig. 1: The RTL-to-GDSII flow showing options available to complete the floorplanning step and its relationship to the entire flow.

Siemens EDA tools incorporate AI in products throughout the entire IC design and manufacturing flow. Siemens’ digital implementation tool, Aprisa, offers a unique AI-driven AMP that lets designers generate a high-quality floorplan in a short amount of time (as short as an hour) compared to any floorplan generated in a traditional manner, which takes weeks or months. The fast runtime is great, but the main benefit is the high quality of the floorplan that mimics how designers would naturally align the blocks. In addition, Aprisa’s AMP keeps track of timing and congestion, pulling macros that can cause issues down the flow to a more optimal location.

These qualities make automated floorplanning a key improvement for designers during their RTL-to-GDSII cycles. Aprisa minimizes the dedicated effort by design experts to place macros, reducing the many iterations to make adjustments based on congestion and timing, and slashes the overall time spent during this step in the flow. The results allow designers to meet their PPA goals faster.

AI-driven macro placement

Aprisa’s AMP offers fully automatic features:

  1. Macro global placement uses Aprisa’s competitive timing-driven engine to naturally place the macros that belong to the same hierarchical module closer together
  2. Macros with the same physical dimension are grouped together to ensure proper alignment and better routability
  3. AMP automatically avoids macro placement that results in unusable space on the chip, ensuring efficient core utilization
  4. Aprisa contains built-in AI-based design algorithms to legalize the macro placement and avoid common floorplanning issues, such as bottlenecks created by narrow channels

Figure 2 shows an example of how Aprisa’s AMP naturally puts macros that belong to the same hierarchical module (modules are noted by a unique color), in close physical proximity to each other, and that most macros are properly aligned. For this testcase, Aprisa’s AMP floorplan achieved 10% shorter wirelength and 15% less leakage power, versus the handcrafted floorplan after full flow final QoR analysis. Timing closure was achieved for both Aprisa’s AMP floorplan and handcrafted floorplan. In terms of runtime, it took around 1 hour for Aprisa’s AMP to generate the floorplan for this design compared to weeks for the handcrafted floorplan.

Fig. 2: Floorplanning comparisons between handcrafted vs. Aprisa AMP vs. open-source AI package, for a sample design.

The right-most image in figure 2 shows how an open-source AI package placed macros on this test design. Although the tool ran fast, it mixed up the macros belonging to different hierarchical modules as it does not have a native alignment mechanism. As a result, the open-source package floorplan had 30% longer wirelength than Aprisa’s AMP floorplan, and using the open-source floorplan, the P&R flow could not close timing for this design.

The quality of Aprisa’s AI-driven AMP comes not only from the initial algorithms that mimics the handcrafted floorplanning methodologies but also from Aprisa’s timing engine.

Improving final QoR

Aprisa’s AMP offers semi-automatic features to improve the final QoR and help the designers find the most optimal macro placement for their specific ICs. These features can be run on top of an AMP generated floorplan, but also allow designers to input their expertise, especially on complex designs where they may have spent several versions fine-tuning to improve their final PPA.

A few of the available semi-automatic features include:

  1. Manual repack on selected macros to fix the remaining bottleneck
  2. Tuning of parameters to explore the best possible floorplan
  3. Manual fixing selected large macros on the chip boundary, and letting the timing-driven engine find the best location for the smaller macros in the middle of the chip

The examples shown in figure 3 illustrate how Aprisa’s semi-automatic large macro fixing achieved additional improvement on timing by finding the most optimal macro placement at the floorplan stage. The table below shows the timing and wirelength for the handcrafted floorplan, the Aprisa AMP floorplan, and the Aprisa floorplan after large macro fixing followed by AMP optimization.

Fig. 3: Comparison between handcrafted floorplan vs. AMP base vs. AMP after pre-fixing large macros.

In the example on figure 3, Aprisa’s AMP placed large macros towards the lower left corner of the design area. Even though this floorplan achieved better timing than the handcrafted floorplan, it has 13% longer wirelength. By fixing the large macros at the boundary of the design area, Aprisa AMP was able to optimize the location of smaller macros in the center the design area. This improvement achieved even better timing, and similar wirelength as the handcrafted floorplan.


Aprisa’s AMP can generate a high-quality floorplan with its fully automatic flow for complex designs containing hundreds of macros. This is possible because the AMP technology is based on Siemens’ Aprisa timing engine and built-in AI-based design algorithms and alignment techniques. Its additional flexible semi-automatic features further improve the final QoR and gives designers the opportunity to reduce their floorplan iterations and effort from weeks or months to only a few hours. It also means that design experts can focus on other aspects of their project metric tradeoffs and requirements.

With Aprisa’s tight pre-route to post-route correlation and AMP technology, designers can confidently determine their PPA metrics as early in the flow as the placement stage. Instead of running a myriad of iterations to find the best possible floorplan, they can utilize some of the saved time to figure out what tradeoff metrics can give them the optimal PPA and TAT for their projects.

This shortens the time designers need to spend on crafting the most optimal floorplan to get the best QoR for even the most complex and advanced node ICs.

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