tag: floorplanning

Ensuring Memory Reliability Throughout the Silicon Lifecycle
By Anand Thiruvengadam - 14 Nov, 2022 - Comments: 0

By Anand Thiruvengadam and Guy Cortez Memories are everywhere in modern electronics. Discrete memory chips account for much of the space on printed circuit boards (PCBs). Embedded memories consume much of the floorplan in system-on-chip (SoC) devices. Many multi-die chip configurations, including 2.5D/3DIC devices, are driven by the need for faster memory access. Designing and verifying memo... » read more

A graph placement methodology for fast chip design
By Technical Paper Link - 09 Nov, 2021 - Comments: 0

Abstract "Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method autom... » read more

NoC Experiences From The Trenches
By Kurt Shuler - 28 Sep, 2021 - Comments: 0

Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition or who maybe do not yet see a need for a change. As with a switch to any new technology, the first hurdles are often simply misconceptions. When new users first evaluate any new technology, they often make the mistake of att... » read more

PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning
By Technical Paper Link - 31 Dec, 2020 - Comments: 0

Academic research paper from Dept. of CSE, IIT Guwahatim, India. Abstract: "With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying ... » read more

Can Machine Learning Chips Help Develop Better Tools With Machine Learning?
By Vinay Patwardhan - 18 Jun, 2018 - Comments: 0

As we continue to be bombarded with AI- and machine learning-themed presentations at industry conferences, an ex-colleague told me that he is sick of seeing an outline of the human head with a processor in place of the brain. If you are a chip architect trying to build one of these data-centric architecture chips for machine learning or AI (as opposed to the compute-centric chips, which you pro... » read more

The Ultimate Shift Left
By Brian Bailey - 09 Mar, 2017 - Comments: 0

Floorplanning is becoming much more difficult due to a combination of factors—increased complexity of the power delivery network, lengthening of clock trees, rising levels of communication, and greater connectedness of [getkc id="81" kc_name="SoC"]s coupled with highly constrained routing resources. The goal of floorplanning is to determine optimal placement of blocks on a die. But connect... » read more

How High-Level Synthesis Was Used to Develop An Image-Processing IP Design From C++ Source Code
By Cadence - 07 Dec, 2016 - Comments: 0

Imagine working long and hard on a design, only to learn that you need to add new (and more complex) functionality a few months before your targeted tapeout. How can you deliver the performance and capabilities expected in the same timeframe? For Bosch, high-level synthesis (HLS) provided the solution. In this paper, we will discuss how HLS technology enabled the team to meet an aggressive sche... » read more

Power Confounds, Challenges
By Ann Mutschler - 14 Jul, 2016 - Comments: 0

I have to admit I’m always surprised to hear that design teams are not using tools to the fullest extent possible, leaving valuable power saving opportunities on the table, until I remember how daunting it is to get it all right without tremendous experience, expertise, and the right tools. I’m also always fascinated to learn about less-obvious effects from power. To this point, Aveek... » read more

Next-Generation RTL Floorplanning
By Mentor, a Siemens Business - 10 Feb, 2016 - Comments: 0

Mentor’s physical RTL synthesis tools, including RealTime Designer and next-generation products, have the unique technology to pull placement ahead of synthesis and address the need for RTL floorplanning. Mentor’s physical RTL synthesis tools offer higher capacity, faster runtimes, optimal QoR, and physical awareness during RTL synthesis by optimizing at a higher level of abstraction and u... » read more

IC Compiler II Multi-Level Physical Hierarchy Floorplanning
By Synopsys - 27 Jan, 2016 - Comments: 0

Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. Synopsys' IC Compiler II provides automation designs with multiple levels of hierarchy that minimizes time to results, provides best QoR, and ... » read more

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