A tool for floorplanning where a flat layout methodology is no longer an option.
As designers strive to pack more and more functionality into todays’ SoC’s, design size (in terms of the number of transistors packed into a chip) is growing almost exponentially. This growth brings with it an unbounded increase in not just the technical complexity of performing the physical layout of the design due to capacity challenges, but also requires designers to make choices that can have profound effects on a design’s ultimate tractability and marketability.
For these large, complex designs, a flat layout methodology is no longer an option. Prohibitive implementation runtime coupled with high memory requirements means that these designs have to be implemented hierarchically in a divide and conquer methodology.
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