A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning

Increasing density makes congestion a challenge for both cities and chips.


What do chip floorplanning and city planning have in common? As it turns out, quite a lot. This was the premise for an award-winning talk given by MediaTek at this year’s Synopsys User Group (SNUG) in Taiwan.

Urban city development was used as an example to understand how utilization rate (UR) and congestion relate to chip planning. UR was defined in the example as population density while congestion was equivalent to a traffic jam. Metropolitan areas with a high UR or population density experience increased congestion or traffic jams if they have poorly planned transportation routes because the roads are ill-equipped to handle the high-volume of people. To reduce congestion despite having high UR, a city would require better transportation planning. MediaTek then cited Singapore as an example of good city planning that alleviates congestion or slows the rate of congestion. Singapore’s city floorplanning created an extensive public rail system that was easily accessible by over 80% of its residents, leading to the ability for its population to travel quickly and efficiently.

Aerial view of Singapore’s transportation floorplan network.

Now, let’s take that example and apply it to chip design floorplanning. Today’s designs are challenged with ever shrinking chip sizes making congestion a very real issue. Advanced node technologies are creating more transistor density, meaning that too many nets are forced to be routed in local regions. This increased density causes long route detours and even un-routable nets when detailed routing is done. This routing congestion can be measured as the difference between required and available tracks.

The utilization rate (UR) in chip design is important because it acts as a score to measure chip competitiveness. The better the UR, the better the chip performance. Chips with low achievable UR experience rapidly increasing congestion as chip size shrinks. Whereas chips with high achievable UR experience a much slower increase in congestion as chip size decreases.

To maximize UR, exploration needs to be done in the early design stage before block shapes and sizes are finalized. Once the power, performance, area (PPA) and UR targets are set, UR exploration is done to identify the best floorplan strategy for each block-level to meet those PPA and UR targets. If the floorplan quality isn’t met, then the designer needs to fine tune the block size and shape and rerun UR exploration. This process is repeated until all targets are achieved. As you can imagine, this process is exhausting. Floorplans must be prepared manually, putting a burden on engineering resources and taking up valuable time. As more iterations occur, the risk of missing tight market windows increases.

Designers need to ask themselves two questions: How do I save run-time while sustaining accuracy during UR exploration? and, How do I improve the UR?

In answer to these questions, MediaTek proposed using Synopsys RTL Architect and its UR-Scout capability. Synopsys RTL Architect uses a fast, multi-dimensional implementation prediction engine that enables RTL designers to predict the power, performance, area, and congestion impact of their RTL changes. As MediaTek points out, Synopsys RTL Architect possesses powerful run-time savings while sustaining accuracy. MediaTek employed Synopsys RTL Architect to perform multiple design space explorations for power-source-equipment. This included: utilization; aspect ratio; shape; tool options; and design parameters related to library, supply power, variable and max routing layer. They were able to launch 8 parallel runs with a single license. The dashboard provided in the solution provided a unified view of the results.

Using Synopsys RTL Architect, MediaTek was able to achieve greater than a 5% performance gap and a 90% run-time savings with respect to advanced place and route tools. They also achieved a 5% improvement in logic density.

To learn more about how MediaTek used Synopsys RTL Architect and the additional results they achieved, download the SNUG presentation.

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