Automation And Correct By Construction Will Empower 3D-IC Adoption


When research on 3D ICs was in full swing around 2009, I had been researching on how through-silicon-via (TSV) was related to thermal in a semiconductor chip-making company, and it seemed logical that 3D ICs would become mainstream. However, during the past 10 years, use of 3D stacked die has been applied to only a few applications, such as memory or image sensors, and the 2.5D solution using i... » read more

The Rising Importance Of Design Planning


Design Planning is often overlooked in the chip design flow. The front-end designer carefully architects the design functionality to produce golden RTL. This is then poured into the synthesis engine to produce logic gates. The synthesized netlist is then thrown over the wall by the front-end designer for physical implementation. The back-end designer receives a gate-level netlist, timing con... » read more

Fusion Compiler Unified Physical Synthesis


This white paper discusses how Fusion Compiler's unified physical synthesis optimization technologies addresses the time-to-market pressure and delivers the quality of results required for advanced process node leading-edge designs. Also learn about how unified physical synthesis seamlessly shares technologies and common engines between synthesis and place-and-route domains to deliver the best ... » read more

Thermal Impact On Reliability At 7/5nm


Haroon Chaudhri, director of RedHawk Analysis Fusion at Synopsys, talks about why thermal analysis is shifting left in the design cycle and why this is so critical at the most advanced process nodes. https://youtu.be/wjkrEFLb2vY » read more

Changing The Design Flow


Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

In-Design Power Rail Analysis


Tech Talk: Kenneth Chang, senior staff product marketing manager at Synopsys, talks about what can go wrong with power at advanced nodes and why in-design power rail analysis works best early in the flow in helping to reduce overall margin. https://youtu.be/0oiWQPS1-Xk » read more

The Ultimate Shift Left


Floorplanning is becoming much more difficult due to a combination of factors—increased complexity of the power delivery network, lengthening of clock trees, rising levels of communication, and greater connectedness of [getkc id="81" kc_name="SoC"]s coupled with highly constrained routing resources. The goal of floorplanning is to determine optimal placement of blocks on a die. But connect... » read more

FinFET And Multi-Patterning Aware Place-And-Route Implementation


The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Nitro-SoC place and route system handles them. To read more, click here. » read more

Timing Closure Issues Resurface


Timing closure has resurfaced as a major challenge at 10nm and 7nm due to more features and power modes, increased process variation and other manufacturing-related issues. While timing-related problems are roughly correlated to rising complexity in semiconductors, they tend to generate problems in waves—about once per decade. In SoCs, timing closure problems have spawned entire methodolog... » read more

The Time Dimension Of Power


Power is the flow of energy over time. While both aspects of that equation are important, they are important to different people in different ways. Energy that moves too quickly can cause significant damage. Too much energy moving over time can mean a non-competitive product, from battery-powered devices to a wide array of locations such as the datacenter. When the industry talks about power... » read more

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