Changing The Design Flow


Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

In-Design Power Rail Analysis


Tech Talk: Kenneth Chang, senior staff product marketing manager at Synopsys, talks about what can go wrong with power at advanced nodes and why in-design power rail analysis works best early in the flow in helping to reduce overall margin. https://youtu.be/0oiWQPS1-Xk » read more

The Ultimate Shift Left


Floorplanning is becoming much more difficult due to a combination of factors—increased complexity of the power delivery network, lengthening of clock trees, rising levels of communication, and greater connectedness of [getkc id="81" kc_name="SoC"]s coupled with highly constrained routing resources. The goal of floorplanning is to determine optimal placement of blocks on a die. But connect... » read more

FinFET And Multi-Patterning Aware Place-And-Route Implementation


The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Nitro-SoC place and route system handles them. To read more, click here. » read more

Timing Closure Issues Resurface


Timing closure has resurfaced as a major challenge at 10nm and 7nm due to more features and power modes, increased process variation and other manufacturing-related issues. While timing-related problems are roughly correlated to rising complexity in semiconductors, they tend to generate problems in waves—about once per decade. In SoCs, timing closure problems have spawned entire methodolog... » read more

The Time Dimension Of Power


Power is the flow of energy over time. While both aspects of that equation are important, they are important to different people in different ways. Energy that moves too quickly can cause significant damage. Too much energy moving over time can mean a non-competitive product, from battery-powered devices to a wide array of locations such as the datacenter. When the industry talks about power... » read more

Case Studies in P&R Double-Patterning Debug


In my last article, we looked at some case studies of the unique types of issues related to double patterning (DP) that place and route (P&R) and chip finishing engineers have to deal with. I’ve got some more interesting case studies to show you this time. In modern P&R designs, the metal routes on a particular layer are unidirectional (or at least primarily unidirectional). Long p... » read more

Tear Down The Wall Between Front-End And Back-End Teams


As complexity of system-on-chip devices increases, it's becoming imperative for design teams and organizations to re-examine how they work with one another in order to improve productivity. One giant step in this direction is to bridge the divide between the front-end design process and the physical back-end design process. We often refer to this as a figurative “wall,” but there is real... » read more

FinFET And Multi-Patterning Aware Place And Route Implementation


The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Olympus-SoC place and route system handles them. To read more, click here. » read more

Case Studies In Double-Patterning Debug


Double patterning (DP) impacts just about every part of the design and manufacturing flows. However, the kinds of issues you encounter, the way they manifest themselves, and the ideal way to address them may be very different in different parts of these flows. I feel like I have spent a lot of time the last six months or so working with place and route (P&R) and chip finishing engineers on DP i... » read more

← Older posts