Shifting signoff verification flows into the design and implementation phases.
The whole is more than the sum of its parts. –Aristotle
A machine is nothing more than a collection of nuts, bolts, wheels, gears, wires, pipes, chains, and what have you. And yet, when they are all connected up properly, magic happens. Instead of a pile of parts, you have a car, or a dishwasher, or a nuclear reactor. The connections and interactions between all those parts turns the whole into something else entirely.
When Calibre Design Solutions began exploring the idea of shifting our trusted integrated circuit (IC) signoff verification flows back into the design and implementation phases, we quickly realized that simply offering access to our signoff tools was not sufficient to provide the productivity improvements required to make such a transition successful. To bring significant value to the designer beyond the verification capabilities built into most design tools, the Calibre nmPlatform would have to introduce new functionalities and capabilities into the design enablement flow:
Driven by that realization, we focused our efforts on four development “pillars” that support and underlay the optimal use of Calibre tools and functionality throughout IC design and implementation, as shown in figure 1. While each pillar is the foundation of one core optimization strategy, together they facilitate a broad new application of Calibre verification that enables design companies to move their layouts from design and implementation to tapeout faster, while improving design accuracy and reliability.
Fig. 1: The four pillars of optimization help ensure a coherent, user-focused verification strategy across the design and implementation flow.
Let’s take a closer look at each of these foundational development pillars, and how they come together to support a comprehensive shift left strategy.
The Calibre nmPlatform is known for innovative leadership in IC design physical verification. Over the years, the Calibre toolsuite has introduced multiple new verification techniques, such as equation-based design rule checking (DRC), pattern-based checking, context-aware reliability checking, and circuit-aware checking, that expanded the boundaries of physical verification to enable design teams to address the growing complexity and advances in IC designs at all process nodes. For shift left we are continuing to broaden the types of verification that enable checking both new types of designs and reliability limiters that previously were only detectable in silicon. Some of these new verification capabilities include power analysis, thermal analysis, and stress analysis for both single chips and 3D stacked packages, as well as support for multigon curvilinear layout construct verification. Not only are these innovative capabilities available, but they are easily deployable in all stages of design and implementation, with the assurance of Calibre precision and accuracy.
The Calibre nmPlatform is continuously enhanced and improved to ensure optimum resource utilization, scaling capacity, and efficient operation. However, if design teams can’t run those tools intuitively, easily, and efficiently embedded in their design tools, they won’t get the productivity they need and expect. As design companies implement shift left strategies, designers and engineers who did not previously interact with Calibre tools may be challenged by the wide range of verification tools, capabilities, and options offered by the Calibre nmPlatform. The key goal of the execution pillar is to introduce a new paradigm for the verification run process that uses intelligent heuristics and models to provide a user-friendly environment that is tailored to the point of use and seamlessly integrated in the design implementation tools. For instance, the optimal setup in early-stage verification relies on a focused set of checks targeting the types of errors most likely to be relevant and useful in incomplete layouts. Comprehensive design flow-centric user interfaces guide and support engineers through the best selection of setup commands and options for their environment. By focusing on the designer’s business needs, the execution pillar “flips” the setup and configuration to improve both the user experience and the effectiveness and efficiency of the software and hardware used.
Designers aren’t paid to run verification tools or fix errors. Their success depends on delivering optimized designs that meet all manufacturing requirements and performance targets as quickly as possible. The more quickly and efficiently designers can sift through large numbers of error results and identify the root causes behind those errors, the more quickly and accurately they can fix them and move their designs forward in the flow. The Debug optimization pillar works to produce more focused and automated debug strategies and technology to simplify and speed up the identification and resolution of design errors. Making Calibre verification debugging more “design-aware” involves identifying specific well-understood design methodology mistakes that cause large numbers of violations, and automatically partitioning those errors into root cause categories, as well as identifying clusters of violations with suspicious feature commonalities that point to a common, but not yet identified, root cause. Even when the exact root cause is not immediately identifiable, these commonalities in identifiable features of violations can be used to help designers sift through results more efficiently and analyze errors as groups, rather than randomly debugging individual errors without any particular strategy. Another key aspect of debug productivity is introducing high-performance interfaces that present debugging information in intuitive, user-friendly formats to dramatically improve debug efficiency.
The Correction optimization pillar looks to build upon our layout analysis engine and signoff-level checking to extend into automating layout modifications to improve design quality. In other words, not only find layout problems during the design phase, but automate layout improvements from many aspects. The Calibre nmPlatform is evolving to take on an ever-broadening set of design correction and optimization functions. Some of the recently released capabilities include insertion of decoupling capacitors (DCAPs) and filler cells, as well as insertion of vias and metal to reduce electromigration (EM) and voltage (IR) drop issues. While most design implementation tools have some layout optimization capabilities, the inherent advantages in the way the Calibre engine processes layouts supports Calibre tools that can automatically perform these layout correction and optimization functions with much faster and more efficient performance. In addition, because Calibre signoff checks can be applied, the results are always “Calibre-correct,” significantly reducing rework at signoff. Calibre tool interfaces and integrations enable designers to apply the same high performance and maximum optimization during the design implementation phase, with all changes back-annotated into the design database.
All this may seem like just a laundry list of random features to you. How, exactly, does it all help you use Calibre functionality earlier in the design flow and reduce time to tapeout?
That is probably best explained using an example. Let’s pick the block placement flow as a portion of the overall design flow to focus in on. Figure 2 shows a typical example of what might happen in this portion of the flow.
Fig. 2: Typical traditional block placement design flow.
Designers generate an initial placement of cells and macros into the initial block design using the place and route (P&R) tool. At this point, many of the macros are probably unfinished and full of errors. As they run the P&R DRC to check the layout, the run takes a long time, and is full of errors that don’t apply to the block designers, as they are mainly focused on the interfaces between the macros and cells at this point.
After a difficult debug session, problems with the placement are discovered and edits made for a second-round placement attempt. Maybe the macros are finished now, but they may still contain errors that have actually been waived by the foundry, but the next round of P&R DRC flags them (because it doesn’t know about the waivers) along with new placement issues.
All these issues are eventually fixed in a third round of placement. Assuming this layout now passes the P&R DRC checks, the designers move on to using the P&R DCAP and filler cell insertion. Another P&R DRC round finds new errors that were created because the P&R cell insertion utility didn’t account for some esoteric constraints, so a second round of cell insertion fixes are required to get the layout to DRC-clean again.
Now it’s time to add base layer dummy fill into the block. The designers use the P&R tool solution for this step, and after P&R DRC finds more issues that are fixed (either by automation or by hand), the P&R DRC tool finally says everything is clean.
The designers finally get to the point in the design enablement flow where they traditionally first think about using Calibre verification. They stream out the block and run Calibre DRC in batch outside the P&R tool, only to discover that the layout is not signoff-clean after all, as the Calibre nmDRC tool finds several subtle issues in placement and fill that the P&R DRC tool missed. Now the designers must go back into P&R and iterate placement and fill to fix all the issues, stream out again, and run Calibre verification one last time to get that final signoff stamp of approval.
Is there a better way? We certainly think so. Figure 3 shows the Calibre shift-left alternative that has the potential to improve that entire flow.
Fig. 3: Calibre shift left block placement design flow.
In the Calibre shift left flow, designers use the Calibre RealTime Digital tool to integrate execution and debug using various Calibre tools right inside the P&R tool, with no requirements to stream out data, run Calibre jobs in batch, or review errors externally. After the first macro and cell placement round, the designers run Calibre nmDRC Recon functionality with graybox capability that automatically turns off checks that don’t apply at this stage of the design. This option lets designers mask out macros that are still in development, but still flag errors at the interfaces to those macros (which are what the designers are most focused on). Because of that much more focused run, the DRC runtime is much faster, and the results are much easier to debug, helping drive the second placement run.
In that second run where the macros are now finished, but have waived errors, the Calibre AutoWaivers tool can be used to automatically remove those errors from the results, helping designers focus on the true errors associated with the placement and interfaces. Accordingly, the second debug is much faster, leading to the final placement round.
After the placement is clean according to Calibre verification, the designers can use the Calibre DesignEnhancer tool to perform the DCAP and filler cell insertion, and the Calibre YieldEnhancer tool to run SmartFill fill insertion (which does a much better and faster job than the built in P&R tools fill). Because those Calibre tools rely on Calibre signoff checks, designers can wait to run the final DRC until those steps are complete, and still get signoff-clean results the first time, eliminating an entire set of iterations. Even better, because the same Calibre engine was used in the early DRC rounds, there will be no discrepancies between the results, so there will be no new errors that require fixing.
In addition to streamlining the design flow, Calibre shift left solutions offer completely new types of verification that were not previously available to block-level designers. Assume, for example, that this block incorporated a compiled memory provided by the foundry. The fear with all third-party intellectual property (IP) is that even if DRC says your layout follows all the rules, you may have inadvertently modified something in the IP that doesn’t break DRC, but now invalidates the certified IP. New Calibre Pattern Matching-based tools use certified pattern libraries provided by the IP vendor to compare the integrated IP and identify any portion that was somehow modified from the certified original. Without this new kind of verification, designers might not find out about these inadvertent modifications until the chip was in silicon and failing in the field. Finding this kind of problem in early stages of the design flow can save significant time and money.
The shift left “miracle” occurs when the expansive capabilities being developed within the four pillars are utilized in new ways upstream in the design flows, enabling a revolution in productivity and design quality. These shift left use models require designers to think about their flows in ways they may never have before, and to be open to considering what the Calibre nmPlatform can bring to their workflow beyond signoff verification. By bringing Calibre to early design and implementation with new tools and technologies, Calibre shift left solutions can enable the production of the high performance, reliable chips that are the foundation of the digital transformations taking place in the world around us.
For a more in-depth discussion of the four pillars, check out our technical paper, The four foundational pillars of Calibre shift left solutions for IC design & implementation flows. For more reading on what a Calibre shift left implementation can do for your company, visit our Shift left with Calibre solutions webpage, and browse our library of resources.
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