Hybrid Prototyping


David Svensson, applications engineer in Synopsys’ Verification Group, explains how a virtual transaction logic model can be connected to develop hardware-dependent drivers before RTL actually exists, why this is now critical for large, complex designs, and how to find the potential bottlenecks and debug both software and hardware. » read more

Automotive Chip Design Workflow


Stewart Williams, senior technical marketing manager at Synopsys, talks about the consolidation of chips in a vehicle and the impact of 7/5nm on automotive SoC design, how to trade off power, performance, area and reliability, and how ISO 26262 impacts those variables. » read more

Design For Airborne Electronics


The Next Generation Air Transportation System (NextGen), an FAA-led modernization of America's air transportation system meant to make flying more efficient, predictable and safer, is currently underway as one of the most ambitious infrastructure projects in U.S. history. This is not just a minor upgrade to an aging infrastructure. The FAA and partners are in the process of implementing new ... » read more

Dealing With ECOs In Complex Designs


Namsuk Oh, R&D principal engineer at Synopsys, talks about the impact of more corners and engineering change orders, how that needs to be addressed in the flow to close timing, and how dependencies can complicate any changes that are required. » read more

Using Static Analysis For Functional Safety


Fadi Maamari, group director for R&D at Synopsys, explains why static analysis is suddenly in demand in auto chip design, how it can help to choose the best implementation of functional safety approaches, and where it fits into the design flow. » read more

Transforming Silicon Bring-Up


Not too long ago, the return of first silicon from the foundry was a nail-biting moment as power was applied to the chip. Today, better verification methodologies, increased use of emulation, and more mature fabrication practices have transformed how teams utilize first silicon. It is about to be transformed again, and there are some interesting possibilities on the horizon. Much of what use... » read more

Thoroughly Verifying Complex SoCs


The number of things that can go wrong in complex SoCs targeted at leading-edge applications is staggering, and there is no indication that verifying these chips will function as expected is going to get any easier. Heterogeneous designs developed for leading-edge applications, such as 5G, IoT, automotive and AI, are now complex systems in their own right. But they also need to work in conju... » read more

The Challenge Of Defining Worst Case


Worst case conditions within a chip are impossible to define. But what happens if you missed a corner case that causes chip failure? As the semiconductor market becomes increasingly competitive — startups and systems companies are now competing with established chipmakers — no one can afford to consider theoretical worst cases. Instead, they must intelligently prune the space to make sur... » read more

Which Verification Engine When


Frank Schirrmeister, group director for product marketing at Cadence, talks about which tools get used throughout the design flow, from architecture to simulation, formal verification, emulation, prototyping all the way to production, how the cloud has impacted the direction of the flow, and how machine learning will impact verification. » read more

Adding Order And Structure To Verification


You can't improve what you can't measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of individuals within an organization, which may affect their ability to adopt certain technologies, and it requires considerable attention. This is where concepts such as capability maturity models (CM... » read more

← Older posts