Fast-Track Your Early SoC Design Exploration And Verification


By Nermeen Hossam and John Ferguson Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as computation, internal communications, and signal processing. These blocks are often built by separate teams or IP suppliers, and integrated into the SoC layout. Howev... » read more

The Growing Uncertainty Of Sign-Off At 7/5nm


Having enough confidence in designs to sign off prior to manufacturing is becoming far more difficult at 7/5nm. It is taking longer due to increasing transistor density, thinner gate oxides, and many more power-related operations that can disrupt signal integrity and impact reliability.  For many years, designers have performed design rule checks as part of physical verification of the desi... » read more

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability


Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to design optimization and finishing. Automated context-aware checking provides designers with actionable results that improve both debugging efficiency and verification precision. Introduction Many p... » read more

Verification At 7/5nm


Christen Decoin, senior director of business development at Synopsys, talks about what’s missing in verification, how is that affected by complex chips such as 7nm SoCs or AI chips, and why more steps need to be done concurrently. https://youtu.be/bz6KyJh67sI » read more

Chip Design For The Age Of New Mobility


In the new age of mobility, vehicles are valued more and more for their electronic features instead of mechanical specifications. As a result, companies that are able to own and optimize the design of these critical electronics will capture more of the available profit. This is bringing traditional automotive manufacturers into the electronics business, while simultaneously attracting tech comp... » read more

Five Rules For Correlating Rule-based And Field Solver Parasitic Extraction Results


There comes a time at every foundry and IC design company when it becomes necessary to run a correlation between a rule-based parasitic extraction (PEX) table and a field solver solution. And when that time arrives, there are a few (five, to be precise) details that will help ensure the correlation produces accurate results. But before we get to those, let’s do a quick refresh on PEX techniqu... » read more

A New Approach To Resistance Extraction For Unconventional Geometries


Unconventional metal structures have begun popping up in integrated circuits (ICs) with increasing regularity, for a number of reasons. The growing demand for integrated cameras and image recognition capabilities has fueled the need for components such as high-quality CMOS image sensors with low noise, high dynamic range, and low power. Technology scaling has also contributed to an increase in ... » read more

Physical Verification In The Cloud


Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud trend closely from the sidelines. We have been cautious and have not embraced Cloud as much as other industries – until now. What changed this year? What is driving design companies and EDA tool ... » read more

Physical Verification For Silicon Photonics: Don’t Panic!


Silicon photonics augments traditional electrical signals in integrated circuits (ICs) with light transmission to speed up data transfer and reduce power consumption. According to MarketsandMarkets, the overall silicon photonics market is worth approximately $774.1M in 2018, and is expected to reach $1,988.2M by 2023, at a CAGR of 20.8% between 2018 and 2023  [1]. Cloud computing is one market... » read more

The Week In Review: Design


Tools Synopsys revealed a power analysis solution for early SoC design as well as signoff-accurate power and reliability closure. PrimePower has reliability as a major focus, expanding power and reliability signoff and ECO closure capabilities from physical awareness to cell electromigration effects. Supported power types include peak power, average power, clock network power, leakage power, a... » read more

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