Let’s Do The (IC Design) Time Warp Again

Start physical verification as early as possible in the design flow and continue to check throughout the process.


For the most part, we’ve all been doing integrated circuit (IC) and system-on-chip (SoC) layout the same way for decades. Designers put together the design, be it intellectual property (IP), block, or full chip, then begin running physical verification. For design rule checking (DRC), this process consists of running all appropriate rule checks for the component on all available layouts. The first time out of the box, this verification usually results in hundreds to even tens of thousands of errors. So next comes an extensive review of all the results, and corresponding layout changes in an attempt to fix each individual reported error. Rinse, wash and repeat. The presumed benefit here is a way to track the burn-down, with the expectation that through each iteration, the total number of reported errors will reduce. Unfortunately (and all too often), subsequent runs can reveal even more errors! This lengthy approach of long verification runtimes, complicated debug stages, and lack of clarity on total progress towards tapeout is no longer working in today’s fast-paced market. What if there was a different way?

It’s a shift to the left, then a fix that’s just ri-i-i-i-ight!

Software companies, including the electronic design automation (EDA) industry, face a similar situation. Software designers tirelessly code all the new required features for a target release. Once all changes are checked in, quality assurance (QA) begins. Not surprisingly, initial reviews identify a large number of bugs. Some bugs are naturally trivial to fix, while others require far more complex adjustments. But, without knowledge beforehand of which bugs require greater time and effort, the natural tendency of most engineers is to tackle the bugs in the order in which they are identified. All too often, this results in some of the biggest issues not getting attention until the end of the release cycle, which in turn means pulling features from the target release.

When you consider a toolsuite like the Calibre nmPlatform, which includes software changes across a huge amount of functionality from DRC to layout vs. schematic (LVS) verification, parasitic extraction (PEX), electrical rules and reliability checks (ERC), and design for manufacturing (DFM) layout optimizations, not to mention manufacturing-side uses like optical process correction (OPC), resolution enhancement technologies (RET), and mask generation…each individual release can comprise a huge amount of change.

Like most great ideas (in retrospect), the solution seems so obvious: Don’t wait for the full release to begin QA. Start QA as early as possible, and continue to check throughout the process as further changes are introduced. Implemented in a digital IC design enablement flow, this approach implies starting physical verification earlier in the complete flow, representing a leftward shift in the time domain of a typical burn-down chart (figure 1). A similar strategy can be applied in the custom IC layout flow: move the verification process into the design process, and focus on identifying the most difficult gross errors as soon as possible.

Fig. 1: A shift left strategy offers multiple benefits to both digital and custom IC design teams.

In both cases, there are several shift left tools and techniques that can help, each associated with specific design styles and approaches.

For custom layout, or for custom edits in a digital design, problems typically arise from human error. The Calibre RealTime interface options allow designers to instantly check the results of their edits in their native design environment against Calibre signoff rule decks, ensuring Calibre-clean corrections.

When it comes to auto-routed digital designs, most issues are also caused by human error, but these errors tend to occur earlier, in the form of placement issues. Examples include library exchange format (LEF) abstracts that are out of sync with the shape of the implemented GDS (causing gaps or unintended overlaps and shorts), fill shapes with layers added to blocks with defined keep-outs for those layers (causing unexpected shorts or density issues), or cells pre-colored for multi-patterning rules that are inconsistent in context with neighboring geometry. These design flaws may seem relatively targeted, but in practice can generate thousands of individual errors across many different checks, and often run very slowly with decreased scaling.

The Calibre nmDRC Recon functionality provides a simple, yet highly effective tactic—targeted checking. Instead of running all checks, it selects the rules that are most likely to generate results local in scope. In other words, it runs only those rules that will generate results that are physically close to the underlying root cause design flaws. By viewing these results as a colormap, designers can quickly focus on the regions with the most errors to more quickly identify root cause.

Obviously, the next concern is what to do about these root causes once identified? As discussed, if applying manual edits to make the fix, designers can use the Calibre RealTime Digital tool to quickly understand if the fix was accurate and appropriate. However, shift left tools can also be used to apply automated fixes. Consider a case where placement problems introduce gaps. In theory, most P&R tools should be able to add filler cells, but those filler cells are of a fixed size. The Calibre DesignEnhancer tool can automatically fill such gaps using proven Calibre SmartFill functionality. The Calibre DesignEnhancer tool can also reduce design cycle time by more quickly implementing tasks that typically require significant time during P&R, such as power via insertion for improved power integrity.

Of course, DRC is only one part of the verification process. Circuit connectivity checking is typically one requirement that is not local in scope. For example, a short in the upper-left quadrant of a design may result in errors in the bottom-right quadrant that are not at all intuitive to designers. The Calibre nmLVS Recon short isolation (SI) feature enables short checking and isolation and can be focused on specific layers or text locations. This feature enables fast, automated tracing and correction of shorted nets.

Like software programs, full-chip IC designs are a combination of elements designed by separate teams in parallel. This amalgamation introduces another challenge: ensuring changes at one level of the design do not negatively impact another level. A common example is finding and fixing top-level routing issues when not all of the lower-level blocks are complete, or vice-versa, ensuring a block is not negatively impacted by routing when the routing is not fully complete. The Calibre nmDRC Recon graybox feature can help here, as shown in figure 2. Designers can specify cells and layers of interest that define regions to ignore, while ensuring all others are checked. While ignoring certain geometries may result in additional errors, these errors can often be automatically removed from the results using Calibre AutoWaivers functionality.

Fig. 2: Using Calibre nmDRC Recon grayboxing and Calibre AutoWaivers waving functionality supports an effective and efficient early design-stage verification process.

These shift left tools and features, among others, can combine to significantly speed up the overall design cycle. Start with the Calibre nmDRC Recon functionality to find and fix initial DRC errors, using grayboxing to either ignore incomplete data within cells while doing top-level routing, or to pull in routing or neighboring connections around block placements when top-level routing is still in flux. The targeted DRC set runs quickly and identifies the critical relevant issues that require fixing.

Once these errors have been corrected, a good next step is the application of Calibre nmLVS Recon SI functionality. The short isolation can be performed using an existing LVS deck, eliminating the need to run a full LVS through comparison. Alternatively, designers can generate a “mini” LVS deck if they want to better capture the connectivity as defined by a typical DRC deck. Solving shorts early greatly reduces the connectivity verification effort in subsequent runs.

Finally, return to DRC. Running either the full signoff deck or all signoff rules except for those previously verified and fixed using the Calibre nmDRC Recon functionality during the first phase, designers can focus on the remaining individual errors requiring final fixes. Of course, there will still be iterations (let’s do the time warp again!) but because key issues were already fixed earlier, the number of time-consuming signoff iterations will be greatly reduced.

These are just a few of the examples of the large shift-left focus currently in place from the Calibre nmPlatform. I encourage all designers and verification teams to explore the benefits shift left can bring to design implementation flows and consider how a shift left implementation could improve both time to market and the quality of the final designs.

For more information about shift left with the Calibre nmPlatform, visit our Shift left with Calibre solutions webpage, and checkout our shift left resource library.

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