tag: design-rule checking

Let’s Do The (IC Design) Time Warp Again
By John Ferguson - 26 Oct, 2023 - Comments: 0

For the most part, we’ve all been doing integrated circuit (IC) and system-on-chip (SoC) layout the same way for decades. Designers put together the design, be it intellectual property (IP), block, or full chip, then begin running physical verification. For design rule checking (DRC), this process consists of running all appropriate rule checks for the component on all available layouts. The ... » read more

Why Curvy Design Now? Less Change Than You Think And Manufacturable Today
By Jan Willis - 19 Oct, 2023 - Comments: 0

A curvilinear (curvy) chip, if magically made possible, would be smaller, faster, and use less power. Magic is no longer needed on the manufacturing side, as companies like Micron Technology are making photomasks with curvy shapes using state-of-the-art multi-beam mask writers today. Yet the entire chip-design infrastructure is based on the Manhattan assumption of 90-degree turns, even though i... » read more

Why Shift Left?
By Michael White - 24 Aug, 2023 - Comments: 0

As every integrated circuit (IC) design company knows, the faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. Meeting tapeout schedules improves a company’s chances of reaching their market targets. But as companies create larger and more complex ICs and move to advanced process nodes, the challenge of achieving t... » read more

Fast, Accurate, Automated Via Insertion During Design Implementation Requires Foundry Rule Compliance
By Jimmy Tien - 10 Aug, 2023 - Comments: 0

As the scaling of silicon technology proceeds, via resistance is becoming a dominant factor in integrated circuit (IC) yield, performance, and reliability. At advanced nodes, interconnects and via dimensions decrease, while the number of metallization layers increases. To moderate the impact of via resistance on yield and reliability and reduce electromigration (EM) and voltage drop (IR) effect... » read more

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster
By Nermeen Hossam - 25 Aug, 2022 - Comments: 0

By Nermeen Hossam and John Ferguson Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a chip is DRC-clean to start their chip assembly and verification. Today’s SoC designers typically start chip integration in parallel with block development.... » read more

Reliable DRC Voltage Text Annotation Means Faster And More Accurate DRC Verification
By Abdellah Bakhali - 14 Apr, 2022 - Comments: 0

As the potential for complex interactions between voltage domains grows significantly with the increase in design density at each new process node, the complexity of spacing checks in design rule checking (DRC) also increases. To minimize these types of risk, many simple spacing checks have evolved to become voltage-aware DRC (VA-DRC) checks that incorporate voltage values to determine the requ... » read more

In-Design Signoff DRC For Productivity Improvement
By Srinivas Velivala - 26 Aug, 2021 - Comments: 0

Microsemi, a wholly-owned subsidiary of Microchip Technology, produces a portfolio of semiconductor and system solutions for communications, defense and security, aerospace, and industrial markets. In addition to high-performance and radiation-hardened analog/mixed-signal integrated circuits, FPGAs, SoCs and ASICs, they also design power management products, timing and synchronization devices, ... » read more

Optimize Physical Verification Cost Of Ownership
By Manoz Palaparthi - 29 Jul, 2021 - Comments: 0

As semiconductor designs continue to grow in size and complexity, they put increasing pressure on every stage of the design process. Physical verification, often on the critical path to tape-out, is especially affected. Design rule checking (DRC), layout versus schematic (LVS), and other physical verification runs take longer as chip size increases. In addition, finer geometries introduce new c... » read more

Fast-Track Your Early SoC Design Exploration And Verification
By Nermeen Hossam - 26 Sep, 2019 - Comments: 0

By Nermeen Hossam and John Ferguson Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as computation, internal communications, and signal processing. These blocks are often built by separate teams or IP suppliers, and integrated into the SoC layout. Howev... » read more

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability
By Sherif Hany - 25 Apr, 2019 - Comments: 0

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to design optimization and finishing. Automated context-aware checking provides designers with actionable results that improve both debugging efficiency and verification precision. Introduction Many p... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2023 SMG   |  Terms of Service  |  Privacy Policy