A New Strategy For Successful Block/Chip Design-Stage Verification

Achieving efficiency in integrated circuit (IC) design while maintaining design quality is not just a goal, but a necessity. Designers constantly strive to strike a balance between ever-tightening time-to-market constraints and the finite resources at their disposal, while ensuring the quality of their designs remains uncompromised. Traditionally, IC design flows have been depicted as a linear process, where each stage is neatly completed before moving on to the next. However, the reality of modern IC design demands simultaneous execution of all levels of system design. This concurrent approach, though essential for meeting strict project deadlines, presents unique verification challenges for block/chip designers.

Enter shift left, or design-stage, verification, which is making waves in the world of IC design. Shift left solutions are empowering block/chip designers by addressing verification challenges posed by concurrent design processes earlier in the design flow, leading to increased productivity, faster time to market and an overall enhancement of design quality.

Embracing the complexities of concurrent design processes

Block and full-chip designers find themselves navigating an intricate dance of concurrent design processes. In many cases, in-house intellectual property (IP) cells are designed in tandem with macro blocks and top-level system-on-chip (SoC) designs (figure 1). This simultaneous execution inevitably leads to overlapping iterations, creating a multitude of verification challenges.

Fig. 1: Simultaneous IP and block/chip integration cycles.

For instance, alterations made to lower-level IP cells can significantly impact pin locations, subsequently affecting routing in top-level block/chip designs. Critical decisions regarding top-level power distribution and clock trees must often be made and signed off before lower-level cells and blocks reach completion. This interdependence results in a constant interplay of iterations at each design level.

Unpacking the unique challenges of block/chip design verification

Taking a closer look at each block/chip integration iteration reveals a complex set of activities and internal iterations. Traditionally, the design creation process unfolds within the realm of the place-and-route (P&R) tool. However, physical verification, static timing analysis and reliability verification often occur in other tools. This workflow requires the constant streaming of data out of the P&R tool, external review/debug cycles and iterative re-entry into the P&R tool.

This process is inherently time-consuming, especially during the initial routing and chip finishing stages in the first block/chip integration round, when the various components are at their most nascent. The first design rule checking (DRC) run at this juncture can yield hundreds of millions of errors, requiring exorbitant runtimes, followed by hours (if not days) of debugging.

Revolutionizing IC design verification with shift left solutions

Recognizing the imperative for more efficient and productive design workflows, Calibre Design Solutions pioneered a series of innovative solutions that shift crucial design verification and optimization activities to earlier stages of the design flow. These solutions can significantly boost designer productivity and accelerate time to market, while elevating the overall quality of the designs, by compressing the overall design flow (figure 2).

Fig. 2: Calibre shift left design solutions enable design teams to enhance productivity and design quality while reducing time to market.

Benefits to block/chip designers: A comprehensive overview

The key benefits for block and chip designers using shift-left design methods and tools include:

• Signoff-quality verification in design implementation
• Early design stage LVS verification
• Early design stage error debug
• Early design stage layout optimization

Signoff-quality verification in design implementation

Early design stage DRC verification has historically been riddled with inefficiencies, such as the numerous irrelevant error checks and violations that often result from immature IP designs. To address this challenge, the Calibre nmDRC Recon tool takes center stage. This tool analyzes the DRC checks and automatically identifies categories that can be safely disabled during initial runs. The outcome of this selective DRC verification is twofold: a substantial reduction in runtimes (figure 3), with an average completion time improvement ranging from 60% to 80% and an increase in designer focus on relevant and critical design-stage error debugging.

Fig. 3: Improvement in DRC run times using Calibre nmDRC Recon targeted checking.

To take workflow efficiency to the next level, Calibre Auto-Waivers functionality enters the fray. Paired with Calibre nmDRC Recon targeted verification, the Calibre Auto-Waivers tool intelligently manages layout verification, suppressing irrelevant DRC errors within IP blocks while keeping the focus on interface issues essential for block/chip designers. This not only enhances designer concentration, but also results in approximately 50% reduced runtimes.

Early design stage LVS verification

Layout vs. schematic (LVS) verification is a crucial component of block/chip design verification. The Calibre nmLVS Recon tool steps up to the plate, offering specialized use models that provide short isolation analysis and short paths debugging, targeted electrical rule checking and compare functions for design-stage circuit verification. Block/chip designers can select areas of particular interest in a design to analyze and target only their most impactful nets. These strategic maneuvers shorten the iteration cycle, allowing designers to attain full signoff closure in significantly less time. Figure 4 shows runtime and iteration reductions obtained using the Calibre nmLVS short isolation use model.

Fig. 4: Decrease in runtimes and potential increase in short-isolation iterations using Calibre nmLVS Recon short isolation use model.

Early design stage error debug

Following early design verification, another substantial bottleneck emerges in the form of the disconnect between DRC error detection and the fixing workflow. Designers start with a comprehensive view of the overall landscape of error results. However, resolving these errors is typically a localized and iterative process within the P&R tool. Verifying those fixes requires streaming out the data and running batch DRC. The Calibre RealTime Digital interface bridges this gap by seamlessly integrating the Calibre nmDRC tool into the P&R tool, enabling designers to make changes locally and verify the fix immediately, without the need to stream out any data. The result is not only a considerable reduction in the number of lengthy debug iteration cycles, but because the process uses qualified Calibre rule decks, fixes remain Calibre-clean throughout the remainder of the design flow.

Early design stage layout optimization

Calibre shift-left solutions extend their reach beyond traditional verification operations, providing design-stage layout optimization. To improve design quality, reliability and manufacturability, the Calibre DesignEnhancer tool has three distinct use models. These models empower designers to enhance or replace P&R chip finishing work for redundant via insertion, redundant power and ground rail metal/via insertion and decoupling capacitor (DCAP) and filler cell insertion. Because these layout modifications are performed using qualified Calibre engines, all changes are correct by construction and Calibre-clean on implementation.

The results speak for themselves. In figure 5, the top two graphs show significant improvements compared to baseline P&R results in electromigration (EM) resistance and voltage (IR) drop when employing the via and power/ground via and metal insertion use models. The bottom graph reveals the speed of the DCAP/filler cell insertion process over multiple iterations. These layout modifications are executed using qualified Calibre engines, ensuring that all changes are correct by construction and Calibre-clean on implementation, saving even more time during signoff and tapeout.

Fig. 5: Benefits of using Calibre DesignEnhancer design stage chip finishing solutions vs traditional P&R solutions.

Verification innovation: Beyond the horizon

Siemens EDA pioneered multi-physics verification solutions for block/chip designers. The mPower tools are a solution for full-chip electromigration (EM) and voltage (IR) drop analysis. With its ability to deliver fast, precise and scalable digital power integrity analysis, the mPower Digital tool opens doors for full-chip workload EMIR analysis, even for the most intricate SoC designs. Thanks to its non-proprietary formats, the mPower Digital tool seamlessly integrates into all design and verification flows, ensuring ease of use. Figure 6 offers a glimpse into the user-friendly mPower GUI, which facilitates quick and straightforward setup, execution, analysis and debugging of full-chip power integrity. Watch our on-demand webinar about mPower Digital here.

Fig. 6: The mPower GUI enables full-chip engineers to quickly and easily run an mPower power integrity analysis and debug the results.

Calibre nmPlatform optimization and automation: Streamlining the workflow

In addition to groundbreaking tool functionality, Siemens EDA places a strong emphasis on continually optimizing and automating the execution environment (figure 7). The Calibre Interactive interface emerges as a key player in this endeavor, facilitating the scheduling, optimization and management of multiple Calibre jobs. The run management screen in figure 7 showcases the capabilities of the Calibre Interactive multi-job manager, offering a clear visualization of the process. The introduction of a reusable hierarchical database (RHDB) eliminates the computation redundancy associated with hierarchical database (HDB) construction during split runs. Traditionally, splitting a full DRC run into separate jobs for parallel execution would require each job to process the input layout and rule deck, creating the HDB required for running checks. The RHDB, on the other hand, allows designers to generate and save an HDB based on the full set of checks and reuse it for each split job. This translates to significant runtime savings during split runs, resulting in a more efficient workflow.

Fig. 7: Calibre Interactive multi-job manager screen and reusable HDB usage for multiple jobs.

Conclusion

Concurrent design processes are the norm in the block/chip design flow. Designers face the formidable challenge of managing the verification of multiple design components simultaneously, leading to a significant number of time-consuming verification iterations. In addition, to ensure the success of their projects, designers must remain vigilant in an attempt to reduce “surprises” during signoff and tapeout due to inconsistencies between multiple tools.

This diligence is far from a trivial responsibility, and it underscores the importance of employing tools like those of the Calibre nmPlatform throughout the entire design verification flow. By using tools that all rely on the same foundry-trusted rule decks and proven high-performance engines, designers not only enhance their ability to catch and resolve critical and systemic issues early in the design process, but also increase the likelihood of a fast and successful tapeout.

For block/chip designers, Calibre shift left solutions usher in a new era of efficiency and productivity. They offer a host of advantages, including streamlined workflows, reduced runtimes, simplified debugging and innovative verification and design optimization options. Collectively, these innovations result in significant gains in efficiency, faster time to design closure and improved design reliability and manufacturability. Embracing the power of Calibre shift left solutions can be the key to unlocking the full potential of IC design in the modern age.

For more information about the tools and processes included in Calibre shift left solutions, visit Shift left solutions for IC design stage verification on Siemens EDA.