Reducing IR And EM Issues With Automated Via Insertion


IR drop and EM issues are significant performance and reliability detractors at advanced nodes. Adding vias is the most effective means of correction, but traditional custom scripts are difficult and time-consuming, and do not guarantee correct-by-construction vias. The Calibre YieldEnhancer PowerVia utility uses manufacturing requirements to perform automated insertion of DRC/LVS-clean vias. R... » read more

Balancing Flexibility And Quality In SRAM Verification


Memory is an essential component of system-on-chip (SOC) designs, especially at advanced nodes. SoCs use a variety of memory block types, such as static random-access memory (SRAM) and dynamic RAM (DRAM), to perform computations. The SRAM blocks, which consist of an assembly of specialized calls that abut or overlap one another in a specific arrangement that complies with the circuit specificat... » read more

Speeding Up Process Optimization Using Virtual Fabrication


Author: Joseph Ervin Director, Semiconductor Process and Integration Lam Research Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patte... » read more

Enhancing IO Ring Checks For Consistent, Customizable Verification


The Calibre PERC IO ring checker framework eliminates manual checking by providing a robust DRC-like environment to verify all IO placement rules with sign-off quality. Running on the first LEF/DEF floorplan, the IO ring checker provides early and full coverage of IO ring placement rules, enabling changes with minimal impact on the layout. Fast, accurate debugging and correction ensures that So... » read more

Fast-Track Your Early SoC Design Exploration And Verification


By Nermeen Hossam and John Ferguson Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as computation, internal communications, and signal processing. These blocks are often built by separate teams or IP suppliers, and integrated into the SoC layout. Howev... » read more

Test Chips Play Larger Role At Advanced Nodes


Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long b... » read more

Week In Review: Design, Low Power


M&A NXP will acquire Marvell's Wi-Fi Connectivity business in an all-cash, asset transaction valued at $1.76 billion. The deal includes the Wi-Fi and Bluetooth technology portfolios and related assets; the business employs approximately 550 people worldwide. The deal is expected to close by calendar Q1 2020. Tools Cadence unveiled a data center-optimized FPGA-based prototyping system, ... » read more

The Rising Importance Of Design Planning


Design Planning is often overlooked in the chip design flow. The front-end designer carefully architects the design functionality to produce golden RTL. This is then poured into the synthesis engine to produce logic gates. The synthesized netlist is then thrown over the wall by the front-end designer for physical implementation. The back-end designer receives a gate-level netlist, timing con... » read more

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability


Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to design optimization and finishing. Automated context-aware checking provides designers with actionable results that improve both debugging efficiency and verification precision. Introduction Many p... » read more

Accelerating Physical Verification Productivity for Advanced Node Designs with IC Validator


Applications such as deep-learning, autonomous driving vehicles, and mobility on 5G networks fuel the need for continuous advancements in IC integration. Growing design complexity, pressure on design cycle time, process advancements and increasing verification requirements are driving the need for faster, more efficient physical verification flows. The current state-of-the-art FinFET processes ... » read more

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