A Reliability Baseline Is Essential For Today’s Complex IC Designs

Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

The Week In Review: Design

M&A Barco Silex, now named Silex Inside, split from parent company Barco in a management buyout in partnership with a group of private investors lead by Dutch investment company Vehold BV. The company will continue its focus on security, video compression, and interface IP, along with design services. Tools & IP Mentor is making a version of its HyperLynx design rule checking tool ... » read more

Calibre Evolves Constantly

I find it truly amazing that despite the constantly changing tide in the digital IC design industry that some tools have remained in that number 1 spot for over a decade. The three tools that immediately come to mind are Synopsys’ PrimeTime and Design Compiler and Mentor’s Calibre. I remember back when I first started covering the industry in the mid-1990s that Quad Design’s Motive sta... » read more

Using Automated Pattern Matching For SRAM Physical Verification

How often have you struggled to verify static random-access memory (SRAM) blocks in your design? And how often, no matter how much time you spend on them, do they end up causing manufacturing issues? Memory is a critical component in today’s SoC designs, often consuming 50% or more of the die area. SRAM blocks are typically assembled in a layout using a set of specific intellectual propert... » read more

Advanced Analog And Mixed Signal Design Continues Pushing The Design Envelope

As PCB design has evolved into its present form with extremely complex boards housing high speed circuitry in very small areas, analog and mixed signal (AMS) and high speed analysis can address the latest design challenges. Analog/mixed signal design More and more products incorporate more than just digital circuitry. The vast majority of products now integrate digital and analog circuitr... » read more

Pattern Matching in Design and Verification

Pattern matching (PM) was first introduced as the semiconductor industry began to shift from simple one-dimensional rule checks to the two-dimensional checks required by sub-resolution lithography. These rule checks proved far more complex to write, hard to code for fast runtimes, and difficult to debug. Incorporating an automated visual capture and compare process enabled designers to define t... » read more

Resetting Expectations On Multi-Patterning Decomposition And Checking

It never ceases to amaze me how much confusion and misunderstanding there is when it comes to multi-patterning (MP) decomposition and checking. I sometimes forget just how new a topic it is in our industry. Because of this short-lived history, and the limited time designers have had to acquire any detailed understanding of its complexity, there appears to be some serious disconnect in expectati... » read more

Raising The IQ Of Your MEMS-Based IC Design Flow

By Nicolas Williams and Qi Jing Internet of Things (IoT) applications depend on smart objects that interact with the real world. So your IoT project is likely to contain ICs that integrate micro electro-mechanical systems (MEMS), such as accelerometers, pressure sensors, motors, and microphones that acquire data for analysis. These projects are finding their way into automobiles, phones, and... » read more

Déjà Vu For CMP Modeling?

One definition of design for manufacturing (DFM) is providing knowledge about the impact of the manufacturing process on a design layout to the designers, so they can use that information to improve the robustness, reliability, or yield of their design before tapeout. Essentially, DFM is about designers taking ownership of the full “lifecycle” of a design, and going beyond the required desi... » read more

Ensuring Optimal Performance For Physical Verification

By accessing the most recently qualified version of foundry rule files, users get the most efficient rule implementations. By adopting the most recent version of Calibre, users get the latest improvements in available operations, operation performance, data hierarchy optimization and total scaling, providing the best possible performance and minimizing runtimes. Design teams running full-chip D... » read more

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