Package Assembly Design Kits: The Future Of Advanced Package Design


Why should there be an interest in Package Assembly Design Kits (PADK) today? For the most part, it is due to the advancement in the accumulation of files forming the PADK now offering a customized heterogeneous design experience that optimizes the device's intended package performance with complete connectivity verification, DRC, and assembly validation. Another primary reason is the ongoing f... » read more

A New Strategy For Successful Block/Chip Design-Stage Verification


Achieving efficiency in integrated circuit (IC) design while maintaining design quality is not just a goal, but a necessity. Designers constantly strive to strike a balance between ever-tightening time-to-market constraints and the finite resources at their disposal, while ensuring the quality of their designs remains uncompromised. Traditionally, IC design flows have been depicted as a linear ... » read more

Improving Semiconductor Yield Using Large Area Analysis


Design rule checking (DRC) is a technique used during chip design to ensure that a device can successfully be manufactured at high yield. Design rules are established based on the limits and variability of equipment and process technologies in use. DRC checking ensures that a design meets manufacturing requirements and will not result in a chip failure or DRC “violation.” Common DRC rules i... » read more

Successful 3D-IC Design, Verification, And Analysis Requires An Integrated Approach


3D-IC designs enable improvements in performance, power, footprint, and costs that cannot be attained in system-on-chip (SoC) and IC design. However, the leap from traditional SoC/IC design to 3D-IC designs brings not only new opportunities, but also new challenges. Siemens EDA provides multiple 3D-IC design analysis and verification functionalities that address the diverse needs of 3DIC des... » read more

Let’s Do The (IC Design) Time Warp Again


For the most part, we’ve all been doing integrated circuit (IC) and system-on-chip (SoC) layout the same way for decades. Designers put together the design, be it intellectual property (IP), block, or full chip, then begin running physical verification. For design rule checking (DRC), this process consists of running all appropriate rule checks for the component on all available layouts. The ... » read more

Why Curvy Design Now? Less Change Than You Think And Manufacturable Today


A curvilinear (curvy) chip, if magically made possible, would be smaller, faster, and use less power. Magic is no longer needed on the manufacturing side, as companies like Micron Technology are making photomasks with curvy shapes using state-of-the-art multi-beam mask writers today. Yet the entire chip-design infrastructure is based on the Manhattan assumption of 90-degree turns, even though i... » read more

A Shift Left Strategy Is One Part Of A Holistic Approach To IC Design Verification


The whole is more than the sum of its parts. –Aristotle A machine is nothing more than a collection of nuts, bolts, wheels, gears, wires, pipes, chains, and what have you. And yet, when they are all connected up properly, magic happens. Instead of a pile of parts, you have a car, or a dishwasher, or a nuclear reactor. The connections and interactions between all those parts turns the whole... » read more

Why Shift Left?


As every integrated circuit (IC) design company knows, the faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. Meeting tapeout schedules improves a company’s chances of reaching their market targets. But as companies create larger and more complex ICs and move to advanced process nodes, the challenge of achieving t... » read more

Fast, Accurate, Automated Via Insertion During Design Implementation Requires Foundry Rule Compliance


As the scaling of silicon technology proceeds, via resistance is becoming a dominant factor in integrated circuit (IC) yield, performance, and reliability. At advanced nodes, interconnects and via dimensions decrease, while the number of metallization layers increases. To moderate the impact of via resistance on yield and reliability and reduce electromigration (EM) and voltage drop (IR) effect... » read more

Context-Aware Analysis Can Automatically Protect Critical Nets And Devices During Fill Insertion


Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly become a critical and essential technology that addresses the increasing complexity of geometrical checks used in both established and emerging integrated circuit (IC) technologies. Traditional electronic design automation (EDA) verification tools handle either the physical verifica... » read more

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