Dealing with new challenges along the Z axis.
3D-IC designs enable improvements in performance, power, footprint, and costs that cannot be attained in system-on-chip (SoC) and IC design. However, the leap from traditional SoC/IC design to 3D-IC designs brings not only new opportunities, but also new challenges.
Siemens EDA provides multiple 3D-IC design analysis and verification functionalities that address the diverse needs of 3DIC design teams, from planning and prototyping to both horizontal and vertical design integration, design rule checking (DRC) and layout vs. schematic (LVS) physical verification, parasitic extraction for electrostatic discharge (ESD) and latch-up (LUP) protection verification, cross-die-aware fill insertion, power domain analysis, thermal analysis, and stress analysis. The capture of design-specific information, such as the layer mapping and placement information for each chiplet, forms the basis for this integrated approach, enabling designers to iterate analysis at varying levels of detail throughout the 3DIC assembly process. Our proven 3D-IC design to verification and analysis solution connects 3D-IC planning to layout automation, 3D physical verification, power analysis, thermal analysis, mechanical analysis, and EM/IR analysis, enabling identification and correction of issues early in the design stage, as well as accurate physical and electrical behavior verification of the 3D-IC package.
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