Physical Verification For Silicon Photonics: Don’t Panic!


Silicon photonics augments traditional electrical signals in integrated circuits (ICs) with light transmission to speed up data transfer and reduce power consumption. According to MarketsandMarkets, the overall silicon photonics market is worth approximately $774.1M in 2018, and is expected to reach $1,988.2M by 2023, at a CAGR of 20.8% between 2018 and 2023  [1]. Cloud computing is one market... » read more

Near-Threshold Issues Deepen


Complex issues stemming from near-threshold computing, where the operating voltage and threshold voltage are very close together, are becoming more common at each new node. In fact, there are reports that the top five mobile chip companies, all with chips at 10/7nm, have had performance failures traced back to process variation and timing issues. Once a rather esoteric design technique, near... » read more

Package Designers Need Assembly-Level LVS For HDAP Verification


While advanced IC packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique package connectivity issues, such as missing or misplaced interposer/package bumps/pads, pin naming and text labeling issues, and the like, require new and enhanced LVS-like verification techniques that can move across the entire package to ensure proper connectivity and perfo... » read more

A Reliability Baseline Is Essential For Today’s Complex IC Designs


Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

HBM Upstages DDR In Bandwidth, Power


For graphics, networking, and high performance computing, the latest iteration of high-bandwidth memory (HBM) continues to rise up as a viable contender against conventional DDR, GDDR designs, and other advanced memory architectures such as the Hybrid Memory Cube. [getkc id="276" kc_name="HBM"] enables lower power consumption per I/O and higher bandwidth memory access with a more condensed f... » read more

Device Pin-Specific Property Extraction For Layout Simulation


As we work through the sub-20 nm design space, the interactions between and effects on devices that are near each other are becoming critical factors in achieving the desired electrical performance. Accurate extraction of device pin-specific properties for modelling these effects is essential to attaining design goals. LVS extraction challenges Layout vs. schematic (LVS) comparison tools prov... » read more

LVS Boxing Helps Designers Knock Out Designs Quickly


Keeping up with the constant demand for better, faster design flow performance while preserving the original layout hierarchy of a design can be very challenging during design verification. Designers must constantly manage tradeoffs between performance, database size, and accuracy. In the early design cycle, using the LVS boxing capabilities of Calibre nmLVS to replace incomplete or missing blo... » read more

Optimization Challenges For 10nm And 7nm


Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032"... » read more

LVS Boxing Helps Designers Knock Out Designs Quickly


Keeping up with the constant demand for better, faster design flow performance while preserving the original layout hierarchy of a design can be very challenging during design verification. Designers must constantly manage tradeoffs between performance, database size, and accuracy. In the early design cycle, using the LVS boxing capabilities of Calibre nmLVS to replace incomplete or missing blo... » read more

You’re Not Alone


All too often we get caught up in our own work and our own issues, thinking no one else could possibly be having as much trouble as we are. The reality is that many, if not most, of the problems and challenges in IC verification are not unique to one design, one team, or one person. The natural reluctance of people to admit they are struggling with some aspect of their job often keeps them from... » read more

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