Ensuring Your Power And Ground Nets Are Correctly Connected

In most chip designs, the power and ground nets are likely your largest and most important nets. If any devices are not properly connected, then you cannot expect them to function as expected. Amongst the many problems that can occur to power and ground involves the connections to the well areas of your design that power all the bulk connections to your devices. Well regions connectivity is often ignored until later in the design cycle, but by then, other design connections may obscure power and ground net connectivity errors. The most common way to check these connections is as an ERC (electrical rules checks) called “soft check”. This article describes the soft check process and provides a methodology to resolve well region connectivity issues efficiently.

Defining the connectivity

Modern designs often use multiple voltage supplies. This adds complexity that makes checking the well connectivity a larger consideration. In analog designs, there is often more focus on the details of the contributions by the well layers to the function and performance of the design. This deeper focus intensifies the need for accuracy in defining this connectivity. Additionally, as process size diminishes every aspect of IC (integrated circuit) design becomes more affected by the analog effects.

Well layers should not be used for conducting signals because they are lower in doping concentration than diffusion layers. There is an inverse relationship between dopant density and resistivity, which suggests well layers are modeled with a higher resistance than diffusion layers. This attribute dictates the use of a different connectivity scheme to avoid high-resistance connections. Referred to as “stamping,” the one-way connection function ties the upper layer to the lower layer without allowing the connectivity from the lower layer to affect other upper layer polygons. From this one-way connection, conflicting shapes can be determined and reported through an ERC soft check. Figure 1 shows a cross section of connecting materials and a well connection error that would be flagged by a soft check.

Fig. 1: Cross section view of connecting materials. The conflicting N+ result is outlined in red.

Connectivity from the diffusion layers to the well layers is a direct, two-layer event. An “N+” implanted diffusion within an N- implanted well region conducts current. Likewise, a “P+” implanted diffusion within a P- implanted well region conducts current. This physical reality requires that the diffusion polygons be separated into selected subsets to accurately apply the shapes that define this connectivity.

The metal layer located closest to the tap diffusion shapes connect through a contact opening layer and is situated above the diffusion layer. The metal and contact layers do not directly take part in the connection to the well, they contribute to the connectivity of the diffusion layer.

In analog designs–where well contribution is a focus–the connectivity below the diffusion layer can be complex. Accurately completing the required connectivity for these designs is not trivial. Figure 2 illustrates the complex connectivity of an analog design.

Fig. 2: Complex analog cross-sectional view of materials. The areas denoted by three question marks (???) are undetermined as to their net ID assignments.

Again, the connectivity from the diffusion layer to the well is direct. Defining a connecting layer is typically not necessary. Several optional features of the soft connection checks in the Calibre nmLVS tool can be useful in the more complex situations of analog designs. To learn more about those optional features, download a full technical paper, “Detecting and debugging soft check connectivity errors.”

Defining soft checks

Most soft check definitions are foundry rules, but if your design includes custom rules, it is typically a best practice to keep them as concise as possible. This will increase the robustness and efficiency of the soft connection definitions and their processing.

The detection of the connectivity conflicts are made possible by one-way—or “soft”—connect definitions in the rules. Additionally, the appropriate soft check statements are required to define which lower (well) layer to return results for. For example, there are typically two soft-connection definitions; one for the NWELL layer, and one for the PWELL layer. The soft check definitions are based upon the soft-connection definitions and report the conflicting shapes.

Soft check reporting

For Calibre, the presence of the soft connect statements will cause stamping conflicts to be concisely reported in the extraction report. Adding the option to report soft checks expands this message in the LVS report file, the extraction report file, and in Calibre RVE—with more details, as shown in figure 3.

Fig. 3: Example soft check result in Calibre RVE.

This expanded report supplies the name of the selected net, and the name(s), or identifiers, of the rejected nets. Within Calibre RVE these net names are hyperlinks you can use to highlight these nets in your design environment.

Soft check debugging

Debugging a soft check issue requires an understanding of what a soft check is reporting. There is more than one net—on the upper layer—attempting to be applied to the lower layer (well) shape. Typically, this issue is caused by an open net in the connectivity of the upper layers. Figure 4 shows an example of an upper-layer connectivity soft check error.

In the example shown in figure 4, by connecting the two Metal 1 shapes, the net above resolves to a single net and the soft check issue is resolved. Another possible but less common cause of conflicts could be a misplaced or mislabeled text.

Fig. 4: Example of an upper-layer connectivity soft check issue.

An aspect to consider in debugging soft check results involves the type of well that is involved. Is the conflicting upper diffusion layer trying to connect to an NWell or PWell layer? Typically, NWell is a drawn layer and therefore each island of NWell is isolated and is a smaller part of the design. A smaller area typically means fewer possible connections and easier to resolve. PWell—in this example method—is determined as everywhere that NWell is not found across the entire design. PWell being (typically) a larger area has more potential for connections and, therefore, for conflicts.

If the upper layer connectivity is correct, then the cause of the soft check error is due to a lower layer separation issue. Figure 5 shows an example of a lower-layer connectivity soft check error.

Fig. 5: Example of a lower-layer connectivity soft check issue.

Therefore, there are only two steps to figure out the resolution of a soft check error.

1. Review the connectivity of the upper layer.
2. If nothing is found in step 1, examine the lower layer separation.

The Calibre RVE results viewer make this examination easier, as shown in figure 6.

Fig. 6: Reviewing soft check issues in Calibre RVE.

From the reported error, we can examine the connectivity of the selected net and rejected nets using the right mouse button over the hyper-texted net names, or identifiers. From this pop-up menu we can access the “Net Info” window about the net of interest.

From the Net Info window, we can see that the rejected net 18 only contains a single layer (ptie). This is a quick test to see that it is missing the connectivity to the materials above the upper (diffusion) layer.

As seen in the layer listing for the selected “gnd!” net, the connectivity has all the materials up to Metal3. Additionally, the lower (well) layer (Psub) is available for highlighting. Figure 7 illustrates with a cross section depiction of this issue.

Fig. 7: Illustration of example. Net 18 was flagged.

Adjusting the viewed layers visually confirms the assessment for this (simple) example, as shown in figure 8, where we can see that this ptie (diffusion) shape is missing the contact that would connect it to the Metal1 and above layers. This confirms that this example has an upper-layer connectivity issue.

Fig. 8: View of example layout with upper-layer connectivity issue.

In another example, when the upper layer connectivity appears properly connected, then it is time to examine the lower layer separation for issues. The same approach used in the earlier case applies to analyzing lower-level soft check issues.

In the Net Info window for the rejected, shown in figure 9, we see that it has connectivity throughout the upper layer materials up to metal7.

Fig. 9: Net Info window in Calibre RVE.

Therefore, the upper layer connectivity appears sufficient.

But, as shown in figure 10, when looking at the upper (diffusion) shapes with the well isolation layer (shown in tan) we see that some of the upper (diffusion) layer shapes are enclosed within the isolation area (shown in yellow) and the conflicting shapes are not (shown in green). Therefore, we can deduce that the conflicting shapes need to be within a well isolation area.

Fig. 10: Design view of an example lower-layer connectivity issue. Conflicting shapes (green) are located outside the well isolation area (yellow).

These examples show very simple cases of connectivity issues that you can find using soft checks. To understand and resolve the soft check issues reported of your own design requires a basic knowledge of how the rules are defined. If you use pre-defined rules, then these examples are good background as to what underlies those instructions. If you are an author for physical verification rules, then use this information as a guideline in your development.

Summary

Including soft checks in your LVS flow is useful for finding and fixing soft connectivity issues between diffusion layers and well (substrate) regions for digital and analog IC designs. Accurate reporting, debugging, and correction of these connectivity errors helps ensure that a design will perform as intended when manufactured, enabling design companies to achieve both their performance and reliability targets and market timelines for their products.