How to speed up debug in early-stage design verification iterations and accelerate tape-out schedules.
Early-stage layout vs. schematic (LVS) and circuit verification typically return large numbers of connectivity errors, which can be a critical bottleneck for both LVS and physical verification flows that require correct connectivity for valid results. The Calibre nmLVS Recon tool targets essential and relevant early-stage circuit verification pain points, such as electrical rule checking (ERC) and soft connection checking (softchk) to enable designers to perform fast, efficient, and focused early-stage LVS runs. The Calibre nmLVS Recon ERC and Softchk functions focus on improving turnaround time and simplifying debugging in early-stage iterations, leading to an overall reduction in tapeout schedules.
The Calibre nmLVS Recon tool is the first circuit verification tool designed specifically to improve early LVS verification and debugging flows while reducing overall IC design verification and debugging time. Historically, running ERC in early design stages is an extensive operation that takes hours, and violations are typically very difficult and time-consuming to debug. The Calibre nmLVS Recon ERC and Softchk functions offer multiple capabilities to simplify and speed up ERC and soft connection checking during early design stages. In addition, the ability to re-use previously generated LVS databases, combined with interactive error fixing with fast, visual fix confirmation enables multiple quick iterations for design compliance and optimization.
With these Calibre nmLVS Recon early design functionalities, designers can entirely change the way they perform circuit verification. Switching from conventionally rigid, inefficient, and time-consuming sign-off LVS runs on dirty or incomplete designs to fast, easy, efficient, and focused Calibre nmLVS Recon runs paves the way to the shortest path to sign-off while ensuring Calibre confidence and quality.
Read the white paper here.
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