tag: debug

Debugging Modern SoCs With Embedded Analytics: Instrumentation, Trace, And Faster Root-Cause Isolation
By Mike Sharp - 12 May, 2026 - Comments: 0

As SoCs chase ever higher performance and power efficiency, their designs have become harder to rootcause and harder to debug. Today’s devices combine billions of transistors with heterogeneous compute blocks and a growing mix of third‑party IPs, so failures can come from anywhere: a corner-case interaction between cores, an integration mistake, a timing assumption that no longer holds, or ... » read more

Transforming DRC Closure At Advanced Nodes
By James Paris - 30 Apr, 2026 - Comments: 0

If you’re working on SoCs at 2 nm or below, you know DRC is a different beast these days. Early in the design, it’s common for DRC runs to dump hundreds of millions—or even billions—of violations at your feet. And that’s when everything is changing fast: block interfaces aren’t fixed and constraints are shifting with every new iteration. Making sense of these massive result sets, fi... » read more

Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)
By Technical Paper Link - 18 Mar, 2026 - Comments: 0

A new technical paper, "ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation," was published by researchers at Intel, Nvidia and Synopsys. Abstract "Integration of CPU and GPU technologies is a key enabler for modern AI and graphics workloads, combining control-oriented processing with massive parallel compute capability. As systems evolve toward chiplet-based archite... » read more

Serial Wire Debug (SWD) Protocol: Efficient Debug Interface For Arm-Based Systems
By Divya Chawla - 12 Mar, 2026 - Comments: 0

Modern embedded systems are becoming increasingly compact, power efficient, and feature rich. As SoCs integrate more functionality, developers need reliable debug access without increasing pin count or board complexity. Serial Wire Debug (SWD) addresses these needs by providing a streamlined alternative to JTAG, enabling high performance debug features using only two pins, making it ideal for t... » read more

Autonomous ASIC Root Cause Analysis
By Mehir Arora - 23 Dec, 2025 - Comments: 0

By Mehir Arora and Zackary Glazewski Over 50% of frontend ASIC hardware engineering time is spent on debugging and root cause analysis, spent churning through millions of lines of code and terabytes of waveform data. Despite this, there are no existing solutions for autonomous root cause analysis that use both code and waveform data. ChipAgents Root Cause Analysis (ChipAgents RCA) is the fir... » read more

Beyond The Core: Tackling System-Wide Debugging For Complex SoCs
By Francisca Tan - 09 Dec, 2025 - Comments: 0

The world of System-on-Chips (SoCs) is evolving – with the advancement of generative AI, the increasing demand for high-performance compute, and the innovative shift towards multi-chiplet architectures, system complexity is advancing at an increased pace. And with complexity comes an even greater challenge: debugging complexity. Silent data corruption, elusive timing-sensitive bugs, and i... » read more

2025 Critical Hardware Weaknesses (Hardware CWE Special Interest Group)
By Technical Paper Link - 29 Aug, 2025 - Comments: 0

A new technical paper titled "2025 Most Important Hardware Weaknesses" was published by researchers at Hardware CWE Special Interest Group. Excerpt "The Most Important Hardware Weaknesses (MIHW) empowers organizations with the knowledge to proactively strengthen hardware security and reduce risks at the source. The 2025 CWE MIHW represents a refreshed and enhanced effort to identify and edu... » read more

LLM-Based Chiplet Design Generation Framework (Univ. of Minnesota)
By Technical Paper Link - 29 Aug, 2025 - Comments: 0

A new technical paper titled "MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging" was published by researchers at the University of Minnesota - Twin Cities. Abstract "As program workloads (e.g., AI) increase in size and algorithmic complexity, the primary challenge lies in their high dimensionality, encompassing computing cores, array sizes, and memory hierarch... » read more

How To Transform Verification Time-To-Results
By Priyank Jain - 28 Aug, 2025 - Comments: 0

The clock is ticking. Your team has just completed another full-chip DRC run on a complex 5nm SoC, and the results are overwhelming: millions of violations across hundreds of blocks. With tape-out deadlines approaching, you need to quickly identify which issues are critical, which are systematic and which blocks require immediate attention. Every day spent in DRC debug is a day delayed to marke... » read more

Optimizing System Production with On-Chip Telemetry and ML-Driven Analytics
By proteanTecs - 12 Aug, 2025 - Comments: 0

Abstract As system companies integrate increasingly advanced chips onto their boards for high-performance markets such as AI, Cloud, Telecommunications, and Automotive, the complexity of system production continues to rise. Ensuring quality, performance, and lifetime reliability while minimizing test costs and production time has become a significant challenge.‍ A new solution addres... » read more

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