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Systematic Methodology To Solve Reset Challenges In Automotive SoCs


Modern automotive SoCs typically contain multiple asynchronous reset signals to ensure systematic functional recovery from unexpected situations and faults. This complex reset architecture leads to a new set of problems such as possible reset domain crossing (RDC) issues. The conventional clock domain and CDC verification methodologies cannot identify such critical bugs. In this paper, we prese... » read more

When Is Verification Done?


Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA. Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until then, verificati... » read more

Better Quality RTL


How do you measure the quality of RTL? Philippe Luc, director of verification at Codasip, talks about identifying bugs, improving the overall quality of the verification, what happens when different blocks are used in a design, and how to improve efficiency in the verification process. » read more

Multicore Debug Evolves To The System-Level


The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches. Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact, so many pro... » read more

Using AI And Bugs To Find Other Bugs


Debug is starting to be rethought and retooled as chips become more complex and more tightly integrated into packages or other systems, particularly in safety- and mission-critical applications where life expectancy is significantly longer. Today, the predominant bug-finding approaches use the ubiquitous constrained random/coverage driven verification technology, or formal verification techn... » read more

Using Verification Data More Effectively


Verification is producing so much data from complex designs that engineering teams need to decide what to keep, how long to keep it, and what they can learn from that data for future projects. Files range from hundreds of megabytes to hundreds of gigabytes, depending on the type of verification task, but the real value may not be obvious unless AI/machine learning algorithms are applied to a... » read more

I’m Almost Done


The city of Belgrade is renovating the street where I live. They are also building a new building next to mine so that I can see the construction work from my balcony. Last week, they blocked the street for some 20 minutes, and people got out of their cars and waited outside for the road to open. The construction workers were not in a hurry, and it seemed like everyone was ok with that, so I... » read more

Increase LVS Verification Productivity In Early Design Cycles


With the innovative Calibre nmLVS-Recon early verification tool, designers can run targeted short isolation analysis and debugging on blocks, macros and chips in early design phases. The Calibre nmLVS-Recon short isolation use model focuses on fast, efficient, prioritized short isolation and short paths debugging. To read more, click here. » read more

Debugging Debug


While semiconductor verification techniques have evolved considerably over the last 25 years, the debug of design problems found during verification has barely changed. New algorithms including machine learning, visualization approaches, and problem solving ideas allow a different approach to debug that saves up to an order of magnitude in debug time. Vtool has introduced Cogita, a next-generat... » read more

Challenges In Using AI In Verification


Pressure to use AI/ML techniques in design and verification is growing as the amount of data generated from complex chips continues to explode, but how to begin building those capabilities into tools, flows and methodologies isn't always obvious. For starters, there is debate about whether the data needs to be better understood before those techniques are used, or whether it's best to figure... » read more

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