Simplifying And Speeding Up Verification


Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

An Eye For An AI


AI comes in multiple forms and flavors. The challenge is choosing the right one for the right purpose, and recognizing that just because AI can be applied to a particular process or problem doesn't mean it should be. While AI has been billed as a ideal solution for just about every problem, there are three primary requirements for a successful application. First, there needs to be sufficient q... » read more

A Different View On Debugging


The classic approach to improve an engineering task that is becoming too complex due to its size and detail is to raise the abstraction of design representation. In this way we plan cities, build aircraft and plan 500M gate SoCs. For example, there is no way an ASIC design could go beyond a few thousand logic gates without shifting abstraction to the Register Transfer Level (RTL) and leveragin... » read more

Inevitable Bugs


Are bug escapes inevitable? That was the fundamental question that Oski Technology recently put to a group of industry experts. The participants are primarily simulation experts who, in many cases, help direct the verification directions for some of the largest systems companies. In order to promote free discussion, all comments have been anonymized, distilling the primary thoughts of the parti... » read more

Capturing Bugs Visually


This paper presents a new way to comprehend complex scenarios, in order to significantly accelerate bug detection and resolution. By defining a new visual language, which creates interaction vertices between the simulation scenarios and the code structure on a single matrix, we offer a novel way to compare multiple cycles. It enables verification engineers to reach solid conclusions regarding a... » read more

The Debug Problem…


While semiconductor verification techniques have evolved considerably over the last 25 years, the debug of design problems found during verification has barely changed. New algorithms including machine learning, visualization approaches, and problem-solving ideas allow a different approach to debugging that saves up to an order of magnitude in debug time. Since the inception of Hardware Desc... » read more

Using Processor Trace At The System Level


The race to process more data faster using less power is creating a series of debug challenges at the system level, where developers need to be able to trace interactions across multiple and often heterogeneous processing elements that may function independently of each other. In general, trace is a hardware debug feature that allows the run-time behavior of IP to be monitored. More specific... » read more

Simulation: Balancing Speed And Debug


There’s an old saying about simulation: “It’s all about the need for speed.” Simulation is the core technology for functional verification of semiconductors, and the demand for higher runtime performance never ebbs. Larger chips require more complex testbenches and much larger test suites since verification grows exponentially with increase in design size. With the diminishing return an... » read more

Building A Safety Verification Flow


Sal Alvarez, senior manager of application engineering at Synopsys, explains how safety verification differs from functional verification, what changes with failure mode effects analysis, and how to determine and verify the effectiveness of safety features. » read more

Speeding Up Verification Using SystemC


Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

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