中文 English

The Power Of Big Data: Or How To Make Perfect 30-Minute Brownies In Only 30 Minutes


You're scrolling online, and the picture stops you in your tracks, grabs you, captivates you. Glistening chocolate pieces are, determinedly yet slowly, oozing down a moist brownie with a crisped-to-perfection, powdered topping. It sits there, confident, flaking lazily onto a bone-white china plate. It looks delicious—mouthwatering—and, apparently, you can make it with just a 30-minute inves... » read more

Enhance IC Reliability Design Verification With Coordinate-Based P2P And CD Checking


Coordinate-based P2P and CD checks with the Calibre PERC reliability platform enable quick early-stage design verification of ESD protection and other IC reliability issues. Using coordinate-based checking minimizes the amount of rule deck coding required, enabling design teams to start Calibre PERC P2P/CD verification very quickly, and understand and debug the results easily. Because P2P/CD ch... » read more

AI-Powered Verification


With functional verification consuming more time and effort than design, the chip industry is looking at every possible way to make the verification process more effective and more efficient. Artificial intelligence (AI) and machine learning (ML) are being tested to see how big an impact they can have. While there is progress, it still appears to be just touching the periphery of the problem... » read more

Measuring The Complexity Of Processor Bugs To Improve Testbench Quality


I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and how can I be confident in the quality of the verification?” There is no easy answer. There are several common indicators used in the industry such as coverage and bug curve. While they are absolutely necessary, these are not enough to reach the ... » read more

Improve Your Verification Methodology: Hunt Bugs Flying In Squadrons


After analyzing bugs on several generations of CPUs, I came to the conclusion that “bugs fly in squadrons.” In other words, when a bug is found in a given area of the design, the probability that there are other bugs with similar conditions, in the same area of the design, is quite high. Processor bugs don’t fly alone Finding a CPU bug is always satisfying, however it should not be an e... » read more

Shifting The Design Paradigm To Improve Verification Efficiency


We are in the midst of a verification crisis manifested by a growing gap between verification efficiency and effectiveness. This crisis cannot be solved through improvements in verification methodologies and techniques alone. Indeed, it requires a philosophical change in the way we approach design, with an emphasis on bug prevention. We refer to this fundamental change as design using intent-fo... » read more

Comparing Formal And Simulation Code Coverage


There is a difference in semantics between code coverage generated from a simulator engine and code coverage generated from a formal engine. This paper seeks to raise the awareness of verification engineers on how best to make use of the code coverage data generated by different verification engines. The paper lays out the reasons for using code coverage and describes how simulation code covera... » read more

Who Will Own Debug?


Recently, I had an interesting conversation with a verification leader of one of the world’s leading semiconductors companies. He has some 150 verification engineers in his organization and the group has been exploring EDA solutions for many years. While we’ve exchanged many ideas about EDA and innovation, one sentence that he said stays in my head: Whoever will own debug, will own th... » read more

Intelligent Waveform Replay For Efficient Debug


There is no doubt that design reuse is essential for today’s massive system on chip (SoC) projects. No team, no matter how large or how talented, can design billions of gates from scratch for each new chip. From the earliest days, development teams have leveraged existing gate level designs and register transfer level (RTL) code whenever possible. The emergence of the commercial intellectual ... » read more

Increasing IP And SoC Debug Efficiency 10X With Intelligent Waveform Reuse


Design and verification reuse lies at the very heart of every modern chip development effort. A system on chip (SoC) project with billions of gates cannot possibly be completed in reasonable time without leveraging blocks from prior projects and commercial intellectual property (IP) offerings. These reused blocks are themselves challenging to develop since they are as large and complex as previ... » read more

← Older posts