Leveraging LLMs To Explain EDA Synthesis Errors And Help Train New Engineers 


A technical paper titled “Explaining EDA synthesis errors with LLMs” was published by researchers at University of New South Wales and University of Calgary.


“Training new engineers in digital design is a challenge, particularly when it comes to teaching the complex electronic design automation (EDA) tooling used in this domain. Learners will typically deploy designs in the Verilog and VHDL hardware description languages to Field Programmable Gate Arrays (FPGAs) from Altera (Intel) and Xilinx (AMD) via proprietary closed-source toolchains (Quartus Prime and Vivado, respectively). These tools are complex and difficult to use – yet, as they are the tools used in industry, they are an essential first step in this space. In this work, we examine how recent advances in artificial intelligence may be leveraged to address aspects of this challenge. Specifically, we investigate if Large Language Models (LLMs), which have demonstrated text comprehension and question-answering capabilities, can be used to generate novice-friendly explanations of compile-time synthesis error messages from Quartus Prime and Vivado. To perform this study we generate 936 error message explanations using three OpenAI LLMs over 21 different buggy code samples. These are then graded for relevance and correctness, and we find that in approximately 71% of cases the LLMs give correct & complete explanations suitable for novice learners.”

Find the technical paper here. Published April 2024 (preprint).

Qiu, Siyu, Benjamin Tan, and Hammond Pearce. “Explaining EDA synthesis errors with LLMs.” arXiv preprint arXiv:2404.07235 (2024).

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