Chip Industry Week In Review

By The SE Staff - 23 Feb, 2024 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Intel officially launched Intel Foundry this week, claiming it's the "world's first systems foundry for the AI era." The foundry also showed off a more detailed technology roadmap down to expanded 14A process technology. Intel CEO Pat Gelsinger noted the foundry will be separate from the chipmaker, utilize third-party chiplets and IP, and leverage... » read more

Chip Industry Technical Paper Roundup: Feb. 19

By Liz Allan - 19 Feb, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=199 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review

By The SE Staff - 16 Feb, 2024 - Comments: 0

By Susan Rambo, Karen Heyman, and Liz Allan. Renesas plans to acquire Altium, maker of PCB design software, for $5.9 billion. In a conference call, Renesas CEO Hidetoshi Shibata cited Altium's PCB design software and digital twin virtual modeling as key components of its future strategy. "I believe it will generate transformational value for our combined customers and our stakeholders," Shib... » read more

HW Security Bug Characteristics in Google’s OpenTitan Silicon Root Of Trust Project

By Technical Paper Link - 15 Feb, 2024 - Comments: 0

A technical paper titled “An Investigation of Hardware Security Bug Characteristics in Open-Source Projects” was published by researchers at NYU Tandon School of Engineering and University of Calgary. Abstract: "Hardware security is an important concern of system security as vulnerabilities can arise from design errors introduced throughout the development lifecycle. Recent works have pro... » read more

Chip Industry’s Technical Paper Roundup: Oct 18

By Linda Christensen - 18 Oct, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=57 /] » read more

Automating The Detection of Hardware Common Weakness Enumerations In Early Design

By Technical Paper Link - 12 Oct, 2022 - Comments: 0

A new technical paper titled "Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design" was published by researchers at NYU, Intel, Duke and University of Calgary. "To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible, such as in RTL designs. ... » read more

Technical Paper Round-Up: May 24

By Linda Christensen - 24 May, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=29 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a ... » read more

A Methodology for Automatic eFPGA redaction

By Technical Paper Link - 20 May, 2022 - Comments: 0

New academic paper titled "ALICE: An Automatic Design Flow for eFPGA Redaction" from researchers at Politecnico di Milano, New York University, University of Calgary, and the University of Utah. Abstract "Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the intell... » read more

Technical Paper Round-up: April 26

By Linda Christensen - 26 Apr, 2022 - Comments: 0

Find all technical papers in Semiconductor Engineering’s library. [table id=23 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a ... » read more

Hardware-Supported Patching of Security Bugs in Hardware IP Blocks

By Technical Paper Link - 22 Apr, 2022 - Comments: 0

New research paper from Duke University, University of Calgary, NYU & Intel. Abstract: "To satisfy various design requirements and application needs, designers integrate multiple Intellectual Property blocks (IPs) to produce a system-on-chip (SoC). For improved survivability, designers should be able to patch the SoC to mitigate potential security issues arising from hardware IPs; for incre... » read more

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Chip Industry Week In Review

Chip Industry Technical Paper Roundup: Feb. 19

Chip Industry Week In Review

HW Security Bug Characteristics in Google’s OpenTitan Silicon Root Of Trust Project

Chip Industry’s Technical Paper Roundup: Oct 18

Automating The Detection of Hardware Common Weakness Enumerations In Early Design

Technical Paper Round-Up: May 24

A Methodology for Automatic eFPGA redaction

Technical Paper Round-up: April 26

Hardware-Supported Patching of Security Bugs in Hardware IP Blocks

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