Fast, Focused Early-Stage Circuit Verification Can Get You To Signoff Faster

Performing efficient early-stage LVS runs to simplify debugging.


Designers everywhere know that with the increasing complexity of integrated circuits (ICs), meeting tapeout schedules has become increasingly difficult. While there are often many reasons for missing tapeouts, one critical component is the significant amount of time needed to run the signoff layout verification cycle, which contributes to overall signoff process duration. Much of this schedule impact can be attributed to growing node-over-node complexity, including increases in design complexity, number of devices and polygons, new device types, and more complex measurements and parameter calculations. With circuit verification rules becoming more complex as a result, design companies are experiencing significant growth in circuit verification operations node-over-node.

Given tapeout time sensitivities, it is now critical that many design issues should be checked prior to signoff verification. However, running full signoff layout vs. schematic (LVS) on incomplete designs not only requires long runtimes, but also results in a huge results database with massive numbers of errors that must be reviewed, resulting in equally cumbersome and time-consuming debugging and error fixing cycles. For example, in early design stages, when design layouts are incomplete or “dirty,” running signoff LVS and circuit verification typically returns large numbers of connectivity errors. Connectivity errors can be a critical bottleneck, not only for LVS, but also for many other physical verification flows that require correct connectivity, such as reliability checks, voltage-dependent design rule checking (DRC), and via/fill insertion. Designers want to run these flows and debug their designs early, but each iteration (and there are typically many) results in thousands, if not millions, of errors that engineers must understand and debug (figure 1). Analyzing all these errors is prohibitive and stressful on designers, especially considering that many of the errors are caused solely by the incompleteness of the design and will simply “disappear” as the design comes together.

Fig. 1: In early design stages, running signoff verification can leave designers struggling to meet deadlines and fixing errors unnecessarily.

Early-stage ERC & soft connection checking

Two primary challenges in circuit verification are electrical rule checking (ERC) and soft connection checking (softchk). Detecting ERC or softchk issues in early design stages using a signoff LVS flow is problematic, because each iteration requires a time-consuming LVS signoff run on an incomplete design and results in numerous errors that are irrelevant in these early design stages. Designers may want to target just a specific design issue, or add a check that just takes minutes to run, but with a signoff run they know they will wait for hours or even days to get the results. Multiplying the total iterations needed by the time required for a signoff run quickly adds up to an unacceptable impact on schedules.

Another frustration that designers face in early design verification is debugging ERC and softchk errors. For example, tracing a violating polygon can require many manual steps, and the information available for incomplete designs doesn’t provide enough guidance to help designers debug these errors more quickly. When faced with thousands of these polygon errors, how much time do designers have to debug each one, especially when they know many of the errors will turn out to be immaterial at this stage in the design flow? It quickly becomes an exercise in futility.

Improving early-stage circuit verification

What’s needed is a completely new checking technology that is intelligent, efficient, and fast in early design stages. One that is focused only on the designers’ needs and actionable errors. The Calibre nmLVS Recon tool is an electronic design automation (EDA) circuit verification tool designed specifically to improve early in-design LVS checking and debugging flows and reducing overall verification and debugging time. With the ability to target essential and relevant early-stage circuit verification pain points, such as short isolation (SI), ERC, and softchk, designers can perform fast, efficient, and focused early-stage LVS runs, making their life much easier.

The Calibre nmLVS Recon tool performs intelligent targeted LVS on incomplete and dirty designs by introducing a radical change in the LVS paradigm [1]. In addition to support for short isolation (SI), which allows designers to easily find and fix layout shorts well before tapeout [2], the Calibre nmLVS Recon tool also supports early ERC and softchk. Historically, running ERC and softchk in early design stages is an extensive operation that takes hours, and violations are typically very difficult and time-consuming to debug. The Calibre nmLVS Recon ERC and softchk targeted functionality can significantly reduce turnaround time and simplify debugging in early design stages.

Calibre nmLVS Recon ERC and softchk functionality

Similar to Calibre nmLVS Recon SI, the ERC and softchk functionality enables designers to execute ERC and softchk faster while using fewer hardware resources, eliminating the need to wait hours to debug and fix results. In addition, because of the additional information provided, debugging is faster and easier. As shown in figure 2, both the Calibre nmLVS Recon ERC and softchk functionalities contain built-in features that enable designers to eliminate ERC and softchk issues quickly and easily from their designs at an early stage.

Fig. 2: Calibre nmLVS Recon ERC and softchk features provide faster turnaround time and easier debugging.

Calibre nmLVS Recon ERC

A single ERC check can take hours to run on incomplete or dirty designs and may require multiple debug cycles. Calibre nmLVS Recon ERC offers multiple capabilities to simplify and speed up ERC during early design.

Rule file execution with selected device recognition for path checking (pathchk) enables standalone ERC runs by automatically executing the minimum operations needed for ERC and pathchk with push-button ease of use, providing reduced turnaround time (TAT) by focusing only on what’s necessary to be addressed at this point. The specific devices selected can also be used in data partitioning among different groups, resulting in additional performance savings. Figure 3 illustrates the time savings on real-world designs.

Fig. 3: Real-world designs using Calibre nmLVS Recon ERC rules file execution shows TAT improvement.

Database re-use enables designers to run ERC checks using previously-generated LVS databases. Running Calibre nmLVS Recon ERC incrementally on existing databases is much faster and efficient simply because previously executed steps, such as connectivity and other operations, are skipped entirely. In addition, performing standalone ERC runs incrementally while re-using an existing database helps isolate the ERC checks from other LVS operations, while also reducing the runtimes of both ERC and the other operations. Figure 4 shows an example of the reduction in runtime that can be achieved with this use model.

Fig. 4: Real-world design using Calibre nmLVS Recon ERC database re-use feature shows significant TAT improvement.

Enhanced LVS path-finding capability and debugging improves debugging by providing designers not only with the ability to isolate the path, but also more information about the path, which eliminates multiple manual steps that designers previously needed to perform to pinpoint and fix ERC violations.

Calibre nmLVS Recon softchk

Similar to the ERC functionality, Calibre nmLVS Recon softchk offers multiple features that reduce TAT and enhance debuggability.

Rule file execution with layer-aware Calibre nmLVS Recon softchk not only lets designers perform focused soft connection checking with automatic selection of the minimum operations needed for softchk, but also partition their designs in multiple ways based on layers.

Database re-use enables designers to run softchk using previously-generated LVS databases, while interactive debugging capabilities and expanded debug information eliminate multiple manual steps that designers perform to pinpoint and fix soft connection violations. Interactive softchk debugging/fixing in the Calibre RVE interface also enables designers to apply edits and fixes to a layout on the fly, similar to the interactive SI debugging process [3].

With the Calibre nmLVS Recon Softchk functionality, designers have a complete, fast, and efficient early-stage soft connection checking flow, as shown in figure 5.

Fig. 5: Complete, fast, and efficient soft connection checking flow using Calibre nmLVS Recon softchk.


As part of a growing suite of EDA early-stage design verification technologies, functionality like the Calibre nmLVS Recon solution provides a new paradigm for early in-design circuit verification, enabling design and verification engineers to move through early-stage circuit verification faster and with fewer iterations, leading to an overall reduction in delivery schedules and time to market. Switching from conventionally rigid, inefficient, and time-consuming signoff LVS runs on dirty or incomplete designs to fast, easy, efficient, and focused Calibre nmLVS Recon runs paves the way to the shortest path to signoff while ensuring design confidence and quality.


  1. Hend Wagieh, “Accelerate time to market with Calibre nmLVS Recon technology” Siemens EDA. Oct 2020.
  1. Raghav Katoch, “Increase LVS verification productivity in early design cycles,” Siemens EDA. Oct 2020.
  1. Raghav Katoch, “Improving productivity with more efficient LVS debug,” Siemens EDA. Sept 2019.

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