Author's Latest Posts


How To Speed Up LVS Verification


Layout versus schematic (LVS) comparison is a crucial step in integrated circuit (IC) design verification, ensuring that the physical layout of the circuit matches its schematic representation. The primary goal of LVS is to verify the correctness and functionality of the design. Traditionally, LVS comparison is performed during signoff verification, where dedicated tools compare layout and sche... » read more

Fast LFD Flows With Pattern Matching And Machine Learning Can Deliver Higher-Yielding Designs Faster


By Wael ElManhawy and Joe Kwan A lithographic (litho) hotspot is a defect on a wafer that is created during manufacturing by a combination of systematic process variation and resolution enhancement technology (RET) limitations. Litho hotspots typically represent severe yield detractors, so detecting and eliminating potential litho hotspots prior to manufacturing is crucial to achieving a com... » read more