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Fast LFD Flows With Pattern Matching And Machine Learning Can Deliver Higher-Yielding Designs Faster

Ways to observe the impact of systematic process variation on layouts to improve yield and product robustness.

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By Wael ElManhawy and Joe Kwan

A lithographic (litho) hotspot is a defect on a wafer that is created during manufacturing by a combination of systematic process variation and resolution enhancement technology (RET) limitations. Litho hotspots typically represent severe yield detractors, so detecting and eliminating potential litho hotspots prior to manufacturing is crucial to achieving a company’s target yield quickly. Embedding litho simulation within the overall design flow enables designers to observe the impact of systematic process variation on their layouts, and to take early corrective action to improve yield and product robustness. Adding pattern matching and machine learning to this process can improve and expedite the results while reducing overall runtime.

Lithographic simulation
A foundry’s process design kit (PDK) encapsulates their technology process information. A litho PDK contains fully-qualified “golden” recipes and models designers can use to run litho-friendly design (LFD) simulations and checks to detect potential litho hotspots in their layout. They can then use design for manufacturing (DFM) tools and methodologies to modify the layout and eliminate these hotspots at a stage in the design flow when changes can be made more easily, without imposing significant changes on the surrounding geometries that could create new issues. This litho hotspot reduction methodology is beneficial to both the design teams and the process and manufacturing teams. Not only does it reduce the time needed to ensure a design is ready for manufacturing, but it also improves the manufacturing process and results [1,2].

Of course, designers always want to simulate and check with full accuracy across an entire chip. However, advanced technology nodes require tighter manufacturing process windows, and the number of patterns at full-chip level increase significantly. The cost for such a high degree of accuracy is measured in long runtimes and heavy resource (CPU) usage. Given the reality of limited computing resources and tight market windows, most design companies no longer find it practical to apply litho simulation to an entire chip using existing techniques.

Fast LFD
DFM technology leaders are always looking for new solutions that provide the desired accuracy, but without the time and resource constraints. Because litho simulation is a computationally expensive operation, a fast LFD (FLFD) solution is now being used to simulate full-chip layouts and large IP blocks. The primary difference between traditional LFD and the FLFD flow is that LFD covers an entire layout, while FLFD selects regions of the design most likely to have candidate litho problematic patterns (Figure 1).


Figure 1. Traditional LFD vs. fast LFD process.

Pattern matching fast LFD (PM-FLFD) and machine learning fast LFD (ML-FLFD) are two different approaches for selecting FLFD simulation regions, as shown in Figure 2.


Figure 2. Machine learning FLFD flow vs. pattern matching FLFD flow.

Pattern matching FLFD
By inserting a PM operation before simulation, designers can create a fast LFD (FLFD) process that only simulates in the vicinity of topologies that somewhat resemble known hotspots, while ignoring all other data.

The PM-FLFD flow selects simulation regions based on a library of hotspots. This library is built by collecting previously known hotspots from different design styles and structures, and then used to identify candidate hotspot locations on a new design. Having a pattern library containing real hotspot candidates is an appropriate way to balance between acceptable accuracy and realistic runtime. It can effectively reduce the overall runtime by reducing the amount of input data [3].

Of course, the process of accumulating a library of appropriate candidate litho hotspots faces the challenge of achieving entire pattern coverage. To accurately select/match candidate regions of litho hotspots on new designs, the hotspot topologies of the PM library must be well characterized [4], including the selection of a pattern radius that properly balances between coverage and performance. Identifying an appropriate radius value usually takes multiple test iterations, as shown in Figure 3. Picking a pattern radius that is too small provides high coverage, but generates too many extra hotspot candidates, which in turn results in unnecessary simulation runtime. Choosing a radius that is too large causes the pattern matching to be too specific to previously known hotspots, and results in poor coverage.


Figure 3. PM radius selection is critical to establishing the accuracy and efficiency of the PM library.

Machine learning FLFD
As opposed to the PM-FLFD flow, which uses a discrete PM library, the ML-FLFD flow selects simulation regions based on the locations predicted by a trained ML model. The ML model learns from a pre-determined set of hotspots and non-hotspots to recognize which pattern structures are potential litho risks and identify unknown patterns as potential hotspots. The selection of the simulation region is a binary classification problem—any layout pattern is classified into either a potential hotspot or a non-hotspot using an ML model. The main strength of the ML model is its ability to predict new hotspots that have not been seen in prior designs.

Model training
Previous ML approaches typically used supervised learning models, such as support vector machines (SVMs) [5,6], and artificial neural networks [7]. Recently, deep learning has been adopted to improve the detection accuracy and runtime. Deep neural networks (DNN) is an ML technique used to perform supervised or unsupervised learning tasks on huge sets of data using a network of cascaded multiple non-linear processing layers. With proper tuning of neural network hyper-parameters and processing of input data, the resulting model becomes a complex model capable of modeling the input data accurately, as well as predicting unseen data with high confidence as well. Deep learning is showing promising empirical results both for accuracy and runtime [8,9].

ML algorithms can be categorized into two main types: supervised and unsupervised. A supervised system is one in which the input training data is labelled, or classified. In an unsupervised system, training data is not labelled, but grouped into clusters, depending on calculated features of the inputs. The ML-FLFD flow presented here uses supervised learning.

A deep neural network is used to train a binary classifier that classifies input layout geometry patterns as either hotspots or non-hotspots. Since the neural network should be able to learn a complex model, non-linearities are added by applying carefully chosen activation functions. For the hidden layers, a rectified linear unit (ReLU) activation function is applied, as it reduces the likelihood of a vanishing gradient. The output layer applies a softmax function that normalizes the output of the two nodes to a probability distribution that adds up to 1 [8,9]. The DNN topology of the network used is shown in Figure 4.


Figure 4. DNN topology.

The dataset used to train the DNN is unbalanced by nature, as non-hotspot and hotspot classes are not represented equally (the non-hotspot class is naturally larger than the hotspot class). This imbalance leads to an accuracy paradox, as the classifier becomes more biased towards the non-hotspot class, but designers can overcome this paradox by using metrics that are robust against unbalanced datasets. An unbalanced dataset can also lead to over-fitting on training data, resulting in poor outcomes on blind data. To overcome over-fitting, the model is trained with over-sampled data by adding more patterns from the hotspot class to compensate for the imbalance caused by the predominance of the non-hotspot class.

Feature extraction
Minor differences in features can be the determining factor between a hotspot and a non-hotspot pattern. Deep learning provides a way for the system to learn which features contribute to the creation of a hotspot, and which do not. A dense representation of the input layout pattern geometries is encoded into a high-dimensional feature vector. Because the input feature vector is large, the deep neural network can be used as an automatic layout feature extractor. The number of nodes per hidden layer in a DNN typically gets smaller, and the DNN starts to learn the features, as input values propagate through the DNN model iteratively while being trained on the known hotspot and non-hotspot patterns.

Layout anchoring
In an ML flow, the input layout must be processed to provide data on which the machine trains or performs prediction. Layout anchoring is a mechanism to sample input designs at locations relevant to hotspot identification. Those sampled locations are used in training and/or prediction. For example, a metal line with a width equal to the minimum DRC width may contain a litho hotspot. This line is sampled and anchors are set on it. Similarly, two metal lines separated with the minimum DRC spacing may contain a spacing hotspot. Those lines are subjected to sampling as well. Figure 5 shows ML anchors for hotspot and non-hotspot data points/samples for a minimum width check (MWC).


Figure 5. ML anchors for hotspot and non-hotspot data points/samples for minimum width checks.

Real-world results
How do PM-FLFLD and ML-FLFLD work in the real world? We tested both flows on a chip layer at the 7 nm technology node. For these experiments, we had access to full-chip designs A, B, C and D, and their corresponding hotspots.

We used hotspots from designs A, B and C to create a PM library of known hotspots/litho problematic patterns. We then optimized the library for accuracy and runtime.

In parallel, we prepared an ML-FLFD model using hotspots from designs A, B and C, as well as sample non-hotspots. Hotspot and non-hotspot data points/samples were selected based on the anchoring and feature extraction parameters. The extracted data/features from the three designs were used to train the ML model.

Design D was our test data for both the PM-FLFD and ML-FLFD flows. For the PM-FLFD flow, we used the PM library to match patterns in Design D and select the simulation regions. These regions contain candidate hotspots matching the previously-known litho problematic patterns stored in the PM library. In the ML-FLFD flow, we used the ML-trained model to predict locations of candidate hotspots on Design D. In addition to identifying patterns that were known hotspots at the time of ML training, the ML-FLFD flow also identified candidate hotspots from new patterns that were not part of the ML training data.

The accuracy of both flows was calculated against the total number of hotspots generated from a full LFD simulation on Design D. Accuracy is measured against both the critical threshold and the important range of the warning threshold. Table 1 shows the accuracy of both flows vs. the total number of hotspots generated from the full LFD simulation.


Table 1. PM-FLFD accuracy & ML-FLFD accuracy on the test design D.

The ML-FLFD flow proved to be very accurate when predicting litho hotspots. For critical hotspots, ML-FLFD accuracy approaches 100%, even for new critical hotspots that were not part of the model training data.

The total simulation area of the regions matched by the PM-FLFD flow or predicted by ML-FLFD flow is calculated as a percentage of the full design area simulated by a full LFD simulation. The simulation area is directly related to the total runtime of the FLFD flow, and is used to give an indication of the reduction in runtime compared to the full LFD simulation. Table 2 shows that the simulation area defined by PM-FLFD flow and ML-FLFD flow and the runtime reduction achieved by each flow are quite similar.


Table 2. Simulation area and runtime by PM-FLFD and ML-FLFD on design D.

Conclusion
At advanced technology nodes, designers use process-aware design flows to gain early knowledge of manufacturing process variation and systematic yield detractors in their layout. Litho simulation identifies hotspots early in the design stage, helping to reduce the time designers need to make their design robust and manufacturing-friendly. However, full litho simulation is very compute-intensive and time-consuming. Alternative techniques are needed to ensure design companies can meet tapeout schedules while ensuring the designs they deliver contain few, if any, litho hotspots created by systematic layout issues.

PM-FLFD and ML-FLFD flows both provide improved hotspot identification accuracy while reducing runtimes and resource usage. PM-FLFD provides a good solution when designers have near-complete knowledge of all hotspot patterns at the time the LFD PDK is created. ML-FLFD introduces the additional benefit of accurately predicting/identifying hotspots in new layout patterns that were not known at the time of PDK development. ML achieves this additional accuracy and prediction capability while maintaining or reducing FLFD runtime.

Design companies looking to ensure or maintain high yields in the advanced technology nodes may want to consider creating PM-FLFD and/or ML-FLFD flows to improve their litho hotspot detection while reducing overall runtimes and delivery schedules.

To learn more, download our new whitepaper, Improve Lithographic Hotspot Detection with Machine Learning.

References
[1] Mark C. Simmons, Jae-hyun Kang, Youngkeun Kim, et al., “A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation”, SPIE (2011), VOL. 7974, 79740M. https://doi.org/10.1117/12.881596

[2] E. Teoh, V. Dai, L. Capodieci, Y.-C. Lai, and F. Gennari, “Systematic data mining using a pattern database to accelerate yield ramp,” Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 905306 (28 March 2014); https://doi.org/10.1117/12.2047307

[3] Jae-hyun Kang, Byung-Moo Kim, et al., “Model Based Hint for Litho Hotspot Fixing beyond 20nm node,” Proc. SPIE 8684, Design for Manufacturability through Design-Process Integration VII, 86840N (29 March 2013); https://doi.org/10.1117/12.2011619

[4] Park, Jinho, NamJae Kim, Kareem Madkour, Wael ElManhawy, et al., “High coverage of litho hotspot detection by weak pattern scoring,” Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 942703 (18 March 2015); https://doi.org/10.1117/12.2087473

[5] Mostafa, Salma, J. Andres Torres, Peter Rezk, and Kareem Madkour, “Multi-selection method for physical design verification applications,” Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797407 (4 April 2011); https://doi.org/10.1117/12.878463

[6] Madkour, Kareem, Sarah Mohamed, Dina Tantawy, and Mohab Anis, “Hotspot detection using machine learning,” 2016 17th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016, pp. 405-409. https://doi.org/10.1109/ISQED.2016.7479235

[7] Ding, Duo, Andres J. Torres, Fedor G. Pikus, and David Z. Pan, “High performance lithographic hotspot detection using hierarchically refined machine learning,” 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Yokohama, 2011, pp. 775-780. https://doi.org/10.1109/ASPDAC.2011.5722294

[8] J.-H. L. Moojoon Shin, “Accurate lithography hotspot detection using deep convolutional neural networks,” Journal of Micro/Nanolithography, MEMS, and MOEMS 15(4), 043507 (18 November 2016). https://doi.org/10.1117/1.JMM.15.4.043507

[9] S. N. T. K. Tetsuaki Matsunawa, “Automatic layout feature extraction for lithography hotspot detection based on deep neural network,” Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810H (16 March 2016); https://doi.org/10.1117/12.2217746

Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services in the Design to Silicon division at Mentor, a Siemens Business. He previously worked at VLSI Technology, COMPASS Design Automation, and Virtual Silicon. Kwan received a BA in Computer Science from the University of California, Berkeley, and an MS in Electrical Engineering from Stanford University.



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