中文 English

Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT)


Abstract: "This paper proposes an ultra-scaled memory device, called `Dynamic Flash Memory (DFM)'. With a dual-gate Surrounding Gate Transistor (SGT), a capacitorless 4F2 cell can be achieved. Similar to DRAM [1], refresh is needed, but high speed block refresh can improve the duty ratio. Analogous to Flash [2], three fundamental operations of “0” Erase, “1” Program, and Read are nee... » read more

Modeling Chips From Atoms To Systems


Complexity in hardware design is spilling over to other disciplines, including software, manufacturing, and new materials, creating issues for how to model more data at multiple abstraction levels. Challenges are growing around which abstraction level to use for a particular stage of the design, when to use it, and which data to include. Those decisions are becoming more difficult at each ne... » read more

Optimizing Tool Integration Is Essential To Design Success


By James Paris and Armen Asatryan The relationship between a place and route (P&R) application and the collection of system-on-chip (SoC) design implementation, analysis, and verification methodologies and tools has always been very much a two-way street. The P&R system is the base, if you will, of design implementation—it takes the virtual and makes it physical. However, it is use... » read more

Design For Manufacturing Best Practices


Manufacturing issues are one of the top reasons that we see warranty returns and loss of market share in the electronics industry. Issues like supply chain failures and printed circuit board assembly (PCBA) production challenges related to design can lead to irreparable damage to a brand’s reputation. It is therefore critical that companies have a design for manufacturability (DfM) protocol i... » read more

Accelerate Time To Market With Calibre nmLVS-Recon Technology


One thing is clear…tapeouts are getting harder, and taking longer. As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS-Recon tool enables design teams to rapidly examine dirty and immature designs to find and fix high-impact circuit errors earlier and faster, leading to an overall reduction in tapeout schedules and time to market. To rea... » read more

Design And Measurement Requirements For Short Flow Test Arrays To Characterize Emerging Memories


Emerging non-volatile memories are becoming increasingly attractive for embedded and storage-class applications. Among the development challenges of Back-End integrated memory cells are long learning cycle and high wafer cost. We propose a short-flow based characterization of Memory Arrays using a Cross Point Array approach. A detail analysis of design requirements and testability confirms feas... » read more

EDA In The Cloud


Michael White, director of product marketing for Calibre physical verification at Mentor, a Siemens Business, looks at the growing compute requirements at 7, 5 and 3nm, why the cloud looks increasingly attractive from a security and capacity standpoint, and how the cloud as well as new lithography will affect the cost and complexity of developing new chips. » read more

Fast LFD Flows With Pattern Matching And Machine Learning Can Deliver Higher-Yielding Designs Faster


By Wael ElManhawy and Joe Kwan A lithographic (litho) hotspot is a defect on a wafer that is created during manufacturing by a combination of systematic process variation and resolution enhancement technology (RET) limitations. Litho hotspots typically represent severe yield detractors, so detecting and eliminating potential litho hotspots prior to manufacturing is crucial to achieving a com... » read more

Week in Review: IoT, Security, Auto


Products/Services Mentor, a Siemens Business, announced the release of the final phase of the Valor software New Product Introduction design-for-manufacturing technology, automating printed circuit board design reviews. The company has integrated DFM technology into the Xpedition software layout application. Arteris IP reports that Toshiba has taped out its next-generation advanced driv... » read more

IC Design: Preparing For The Next Node


The challenges of preparing for the next process node require constant preparation by the foundries, the EDA industry, and the design companies. Learn how Mentor works to prepare the Calibre nmPlatform for each “next node,” and ensure that its customers have the tools and performance they need to succeed. To read more, click here. » read more

← Older posts