DSA Re-Enters Litho Picture

By Mark LaPedus and Ed Sperling Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography. Intel continues to have a keen interest in [gettech id="31046" t_name="DSA"], while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn't like a traditional [getkc id="80" kc_name="... » read more

The Next 5 Years Of Chip Technology

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of [getentity id="22820" comment="Lam Research"]; Mark Dougherty, vice president of advanced module engineering at [getentity id="22819" comment="GlobalFoundries"]; David Shortt, technical fellow at [getentity id="22876" co... » read more

Variation Spreads At 10/7nm

Variation between different manufacturing equipment is becoming increasingly troublesome as chipmakers push to 10/7nm and beyond. Process variation is a well-known phenomenon at advanced nodes. But some of that is actually due to variations in equipment—sometimes the exact same model from the same vendor. Normally this would fall well below the radar of the semiconductor industry. But as t... » read more

Overlay Challenges On The Rise

The overlay metrology equipment market is heating up at advanced nodes as the number of masking layers grows and the size of the features that need to be aligned continue to shrink. Both ASML and KLA-Tencor recently introduced new [getkc id="307" kc_name="overlay"] metrology systems, seeking to address the increasing precision required for lines, cuts and other features on each layer. At 10/... » read more

Searching For EUV Mask Defects

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this technology can be used in production. One lingering issue that is becoming more worrisome is how to find [gettech id="31045" comment="EUV"] mask defects. That isn't the only issue, of course. The industry continues to work on the power source and resists. Bu... » read more

Looming Issues And Tradeoffs For EUV

Momentum is building for extreme ultraviolet (EUV) lithography, but there are still some major challenges to solve before this long-overdue technology can be used for mass production. [gettech id="31045" comment="EUV"] lithography—a next-generation technology that patterns tiny features on a chip—was supposed to move into production around 2012. But over the years, EUV has encountered se... » read more

Unsolved Litho Issues At 7nm

By Ed Sperling & Mark LaPedus EUV lithography is creating a new set of challenges on the photomask side for which there currently are no simple solutions. While lithography is viewed as a single technology, [gettech id="31045" comment="EUV"] actually is a collection of technologies. Not all of those technologies have advanced equally and simultaneously, however. For example, aberrations... » read more

Inside Panel-Level Fan-Out Technology

Semiconductor Engineering sat down to discuss panel-level fan-out packaging technology with Tanja Braun, deputy group manager at the Fraunhofer Institute for Reliability and Microintegration IZM, and Michael Töpper, business development manager at Fraunhofer IZM. Braun is responsible for the Panel Level Packaging Consortium at Fraunhofer IZM, as well as the group manager for assembly and encap... » read more

What’s Changing At BACUS

Jim Wiley, president of SPIE BACUS, talks about this year's merger of the EUV Lithography Symposium and the SPIE Photomask Conference—including what's new and different, the latest updates on the event location, and topics to look forward to such as EUV mask inspection—as well as his predictions on machine learning. https://youtu.be/GNxUmMAU9zs » read more

What’s After FinFETs?

Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it's still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next. The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process ... » read more

← Older posts