tag: lithography

Scalable Photomask Optimization With Morphological Learning (SUNY Buffalo, VU, IBM)
By Technical Paper Link - 18 May, 2026 - Comments: 0

A new technical paper, "MorphOPC: Advancing Mask Optimization with Multi-scale Hierarchical Morphological Learning," was published by researchers at University at Buffalo, Villanova University, and IBM T. J. Watson Research Center. Abstract "As feature sizes shrink to the nanometer scale, accurately transferring circuit patterns from photomasks to silicon wafers becomes increasingly chall... » read more

eBeam Initiative At SPIE ALP 2026: Continuing Progress On Curvilinear, EUV, And Data Challenges
By Jan Willis - 16 Apr, 2026 - Comments: 0

The eBeam Initiative’s annual lunch at SPIE Advanced Lithography and Patterning has long served as a focal point for eBeam technology education for the industry. This year marked our 17th gathering, with approximately 150 attendees joining us. As in past years, the value of the session was less about any single topic and more about the collective signal across different parts of the ecosystem... » read more

Exploring The Frontiers Of Lithography And Patterning: Highlights From SPIE Advanced Lithography + Patterning 2026
By Travis Brist - 19 Mar, 2026 - Comments: 0

Leading‑edge system-on-chip (SoC) designs at deep submicron nodes are stretching lithography and patterning capabilities across the entire manufacturing flow. Extreme ultraviolet (EUV) lithography has become central to printing advanced features, using high‑power pulsed lasers to generate a plasma light source and reflective optics to project mask patterns onto the wafer. As error budgets t... » read more

Enabling the Industry’s First GPU-Accelerated Manufacturing Platform
By Synopsys - 19 Feb, 2026 - Comments: 0

Discover how modern chip designs are revolutionizing the lithographic process, driving the need for innovative solutions to meet the industry's demand for shorter design cycles. This whitepaper explores the significant role of GPUs in accelerating computational lithography, offering unprecedented speed-ups for EDA tools in chip development. Learn about the collaborative efforts of Synopsys, NVI... » read more

Early Zone Correction for Enhanced Overlay Precision in Next-Generation FOPLP Lithography
By Onto Innovation - 13 Jan, 2026 - Comments: 0

AI chiplet architectures are driving advanced IC substrates (AICS) toward larger panels, finer line/space, and much tighter overlay budgets. This study presents a lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction (EZC) to reduce alignment-solution errors, the largest item in the lithography overlay budget. In this st... » read more

Expert Panel Sees History Of Continuous Photomask Innovations As Key To The Future
By Jan Willis - 27 Oct, 2025 - Comments: 0

The eBeam Initiative conducted its 14th annual eBeam Initiative Luminaries survey in July and reported the results on September 23, 2025 to more than 200 attendees at its annual meeting during the BACUS SPIE Photomask Technology conference. Industry luminaries representing 51 companies from across the semiconductor ecosystem—including photomasks, electronic design automation (EDA), chip desig... » read more

Charting The Frontiers Of Photomask Technology And Extreme Ultraviolet Lithography
By Travis Brist - 23 Oct, 2025 - Comments: 0

The enormous computing demands of AI and high-performance computing (HPC) applications are putting intense pressure on every aspect of chip development. Challenges arise during architecture, design, and verification, persist through the manufacturing process, and extend to post-silicon lifecycle management as chips are deployed in the field. Lithography, the fabrication step of shining light... » read more

Research Bits: Sept. 16
By Jesse Allen - 16 Sep, 2025 - Comments: 0

Beyond-EUV resists Researchers from Johns Hopkins University, East China University of Science and Technology, École Polytechnique Fédérale de Lausanne (EPFL), Soochow University, Brookhaven National Laboratory, and Lawrence Berkeley National Laboratory propose a combination of new resist materials and a higher-powered EUV process that could enable smaller chip feature sizes. The "beyond... » read more

Nanofabrication Protocol That Allows Patterning Metallic Electrodes on 2D Materials Reliably (KAUST, National University of Singapore)
By Technical Paper Link - 25 Aug, 2025 - Comments: 0

A new technical paper titled "High-yield photolithography protocol to pattern metallic electrodes on 2D materials without adhesive metallic layers" was published by researchers at KAUST and National University of Singapore. Abstract "When using two-dimensional (2D) materials to build electronic devices, adjacent metallic films need to be deposited to form electrodes. However, weak adhesion ... » read more

GPU Acceleration Of Rigorous Lithography Simulations
By Wolfgang Demmerle - 24 Jul, 2025 - Comments: 0

Producing modern semiconductor devices is an immensely challenging process. Successful execution entails advanced process nodes, novel device architectures, new materials, and many fabrication steps. One especially challenging area is lithography, in which light is sent through a photomask, passes through a projection system of lenses and mirrors, and strikes the substrate to create the device ... » read more

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