tag: lithography

Litho Patterning of Conformal Thin-Film Coatings on Complex 3D Structures (KTH Royal)
By Technical Paper Link - 20 Jul, 2026 - Comments: 0

Researchers at KTH Royal Institute of Technology published a technical paper titled “Lithographic patterning of conformal thin films on 3D structures using Scaffold-architected Lift-off masks.” Abstract Excerpt: “Here we present a robust approach for patterning of conformal thin-film coatings on complex 3D structures.” “It is agnostic to the used thin-film deposition process and en... » read more

Accelerating Computational Lithography With GPU Rasterization
By Loay Hegazy - 02 Jul, 2026 - Comments: 0

By Loay Hegazy, Mohamed Taher, and Sherif Hammouda Semiconductor manufacturing at advanced nodes has become a race against physics. Even as feature sizes shrink, the tools that design and validate these circuits must operate with precision and speed. We show in a recent research paper that one part of the post-tapeout flow, rasterization, can be significantly sped up by deploying GPUs for ma... » read more

A Massively Parallel GPU Rasterizer for Next-generation Computational Lithography
By Siemens EDA - 01 Jul, 2026 - Comments: 0

Computational lithography, critical for advanced semiconductor manufacturing, demands high-performance rasterization to meet nanometer-scale precision. Traditional CPU-based rasterizers struggle with the increasing complexity and data volumes of modern designs. This paper presents a massively parallel GPU rasterizer designed to accelerate high-resolution mask synthesis, lithography simulation, ... » read more

Optimizing Curvilinear OPC: Vector- Based Site and Anchor Decoupling
By Siemens EDA - 24 Jun, 2026 - Comments: 0

As semiconductor technology advances to sub-5 nm nodes, curvilinear mask features are essential for pattern fidelity but challenge traditional OPC methods. Siemens introduces an advanced vector-based site and anchor decoupling framework that independently and dynamically controls OPC fragmentation and optimization. This innovation significantly boosts process window robustness, speeds up mask r... » read more

Refining Vision-Language Models For Lithography Defect Detection
By Technical Paper Link - 12 Jun, 2026 - Comments: 0

Researchers from Hanyang University, Korea University, and Korea Institute of Industrial Technology have published “Failure-Aware Refinement of Vision-Language Model for Lithography Defect Detection”. Abstract “Semiconductor lithography inspection requires reliable detection of small pattern defects such as bridge, burr, pinch, and contamination. In this study, we propose ... » read more

Scalable Photomask Optimization With Morphological Learning (SUNY Buffalo, VU, IBM)
By Technical Paper Link - 18 May, 2026 - Comments: 0

A new technical paper, "MorphOPC: Advancing Mask Optimization with Multi-scale Hierarchical Morphological Learning," was published by researchers at University at Buffalo, Villanova University, and IBM T. J. Watson Research Center. Abstract "As feature sizes shrink to the nanometer scale, accurately transferring circuit patterns from photomasks to silicon wafers becomes increasingly chall... » read more

eBeam Initiative At SPIE ALP 2026: Continuing Progress On Curvilinear, EUV, And Data Challenges
By Jan Willis - 16 Apr, 2026 - Comments: 0

The eBeam Initiative’s annual lunch at SPIE Advanced Lithography and Patterning has long served as a focal point for eBeam technology education for the industry. This year marked our 17th gathering, with approximately 150 attendees joining us. As in past years, the value of the session was less about any single topic and more about the collective signal across different parts of the ecosystem... » read more

Exploring The Frontiers Of Lithography And Patterning: Highlights From SPIE Advanced Lithography + Patterning 2026
By Travis Brist - 19 Mar, 2026 - Comments: 0

Leading‑edge system-on-chip (SoC) designs at deep submicron nodes are stretching lithography and patterning capabilities across the entire manufacturing flow. Extreme ultraviolet (EUV) lithography has become central to printing advanced features, using high‑power pulsed lasers to generate a plasma light source and reflective optics to project mask patterns onto the wafer. As error budgets t... » read more

Enabling the Industry’s First GPU-Accelerated Manufacturing Platform
By Synopsys - 19 Feb, 2026 - Comments: 0

Discover how modern chip designs are revolutionizing the lithographic process, driving the need for innovative solutions to meet the industry's demand for shorter design cycles. This whitepaper explores the significant role of GPUs in accelerating computational lithography, offering unprecedented speed-ups for EDA tools in chip development. Learn about the collaborative efforts of Synopsys, NVI... » read more

Early Zone Correction for Enhanced Overlay Precision in Next-Generation FOPLP Lithography
By Onto Innovation - 13 Jan, 2026 - Comments: 0

AI chiplet architectures are driving advanced IC substrates (AICS) toward larger panels, finer line/space, and much tighter overlay budgets. This study presents a lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction (EZC) to reduce alignment-solution errors, the largest item in the lithography overlay budget. In this st... » read more

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