Charting The Frontiers Of Photomask Technology And Extreme Ultraviolet Lithography

The enormous computing demands of AI and high-performance computing (HPC) applications are putting intense pressure on every aspect of chip development. Challenges arise during architecture, design, and verification, persist through the manufacturing process, and extend to post-silicon lifecycle management as chips are deployed in the field.

Lithography, the fabrication step of shining light on a substrate through a photomask to control exposure, has evolved dramatically to meet these challenges. One measure of how much activity is taking place in this space is number of recent blog posts on such topics as general trends in lithography, speeding up computational lithography, and using GPUs in lithography simulations.

Another measure of this topic’s importance is the number of innovative papers presented at every related technical conference. The recent SPIE Photomask Technology + Extreme Ultraviolet Lithography event in Monterey, California, was a great example. Engineers from Synopsys and collaborative partners presented four noteworthy talks.

Virtual fabrication of a 3nm gate-all-around inverter

The notion of the “digital twin” has gained favor in recent years, especially as chip fabrication times have increased. Experimenting with new processes, including lithography, by actually building silicon takes far too long and is much too expensive. Simulating with an accurate digital twin enables a “virtual fabrication” that provides answers in days rather than months.

The Synopsys engineers presented the motivation for a patterning digital twin (PDT), noting that silicon development cycles have grown from 24 to 36 months, as the time for each wafer experiment has grown from 3 to 6 months. Pulling the cycle back toward two years can be accomplished only by using a PDT to guide wafer experiments.

The group chose a gate-all-around (GAA) inverter as the test case. Requiring 10 lithography masks and more than 400 process steps, fabricating this device could not be the primary means of development. Instead of physical wafer fabrication, the study employed simulation with a PDT, utilizing stochastic modeling to conceptualize the impact of process variations. The stochastic simulations incorporated variations in the lithography process, including resist, exposure, and overlay processes.

This study focused on a randomized variation of the overlay. The simulations revealed instances of a broken M0 resist pattern, which resulted in a power-ground short with low resistance. After adjusting the line widths and lengths, further simulations confirmed that the shorts had been resolved. Consequently, PDTs enable the identification and resolution of design and manufacturing issues without the need for physical wafer fabrication, thereby saving time and manufacturing costs.

Multilayer defects: Impact on aerial image through focus

Simulation is also able to assess the impact of defects within an extreme ultraviolet (EUV) mask multilayer (ML), thereby avoiding catastrophic impacts on the device. EUV photomasks consist of a multilayer manufactured one layer at a time, with each layer presenting an opportunity to disrupt aerial image formation and cause errors on the wafer.

At the SPIE event, engineers from Synopsys and Intel described how they used simulation to systematically investigate the relationship between multilayer defect characteristics and their corresponding impact on lithographic performance. They considered possible defect locations relative to mask features (center of adjacent space, at the feature edge, and directly under) and at varying depths within the 163 layers (top, shallow, middle, deep, and at the bottom substate).

Their approach involved placing a spherical defect of varying size at a selected layer in the mask ML, generating the ML using the Stearns defect propagation model, running a full 3D mask simulation, computing the aerial image, and extracting the image contour. The study correlated two experimental defects and their effects to the simulation results: an edge type defect on a vertical line/space pattern and a corner defect on a via pattern.

The results showed that, for both types of defects, experimentally measured results from commercial EUV masks and simulated aerial images matched very closely. The engineers concluded that ML defect size and depth have a complex and counter-intuitive role in determining lithographic impact. They emphasized the importance of understanding these relationships for developing more sophisticated defect classification schemes and improving mask quality control.

Rigorous calibration and validation of high sigma defect prediction models

As in the previous paper, stochastic models are often used within EUV lithography simulations. Accurate prediction of patterns susceptible to rare stochastic failure is a key goal for EUV lithography modeling. One challenge is that calibrating accurate stochastic models require massive metrology data.

In this presentation, engineers from Synopsys noted that the full EUV process window (PW) must consider both traditional and stochastic variations. Traditional PW calculations consider edge variations across field, wafer, and lot. Stochastic effects cause additional local edge variation, resulting in a shrinking of the traditional process window.

Rigorous Monte Carlo stochastic results in a probability map, but this is expensive. 10,000 simulations may be needed to produce just one map. This talk offered an alternative approach: using internal rigorous continuous simulation metrics to match probabilistic lithography results. Both probabilistic models and Monte Carlos stochastic models were generated from wafer defect data.

The study showed a very strong match between the results for the two types of models. The engineers concluded that a combination of traditional and machine learning model calibration methodologies can be used to train full-chip compact models to accurately match rigorously-generated stochastic models enabling full-chip detection and repair of rare stochastic defects.

High-NA EUV optical proximity correction modeling flow: From data preparation to model validation

The final topic from the SPIE event was a presentation by engineers from Synopsys and imec on some of the challenges of performing optical proximity correction (OPC) in high numerical aperture (high NA) EUV manufacturing at advanced nodes. This technique is essential to compensate for image distortions that would otherwise compromise the patterns on silicon.

One common link between this talk and the others is the critical importance of modeling data. There are always tradeoffs between highly accurate models that take a long time to execute and compact models that can produce well-correlated results even at the full-chip level. This particular study focused on resist models for metal oxide resist (MOR), where rigorous physics-based models are expensive.

The team concluded that rigorous models could effectively capture MOR toploss and resist 3D (R3D) deformation, providing valuable insights for modeling compact sub-resolution assist features (SRAF) and hotspot modeling. The results demonstrated that incorporating a layout density map could improve the correlation between rigorous and compact models by 15%.  Additionally, the quality of the compact model met the precision requirements for OPC applications at advanced nodes.

Conclusion

All four of the presented papers showed clearly that lithography experimentation can be “shifted left” to produce results earlier and minimize fabrication turns. The successful adoption of this approach relies on models that are both accurate and fast. Read the full conference papers and learn more here.