Surface Modification for III-V Selective Area MBE of Non-Selective Mask Materials (UT Austin, Harvard)


Researchers from University of Texas at Austin and Harvard University published “Surface Modification for III-V Selective Area Molecular Beam Epitaxy of Non-Selective Mask Materials”. Abstract Excerpt “Selective-area embedded regrowth of III-V semiconductors by molecular beam epitaxy enables the seamless integration of metals and dielectrics into crystalline material for novel... » read more

Curvilinear Masks Push The Limits Of Inspection And Metrology


Key Takeaways: Curvilinear masks require native data flows across design, mask data prep, writing, inspection, and metrology. Inspection is shifting from finding all defects to identifying which mask variations actually print on wafer. High-NA EUV will intensify inspection challenges, particularly for small printable defects and actinic contrast limits. Experts at the table:... » read more

Mask Technology Faces A New Set Of Challenges


Key Takeaways: Mask inspection and repair remain the critical bottleneck, even as multi-beam writers have reduced mask-writing constraints. Curvilinear masks are becoming viable for critical layers, but qualification, metrology, and inspection standards still lag production needs. Scaling curvilinear requires curvilinear-native data flows, model-based checks, GPU/HPC compute, and les... » read more

Scalable Photomask Optimization With Morphological Learning (SUNY Buffalo, VU, IBM)


A new technical paper, "MorphOPC: Advancing Mask Optimization with Multi-scale Hierarchical Morphological Learning," was published by researchers at University at Buffalo, Villanova University, and IBM T. J. Watson Research Center. Abstract "As feature sizes shrink to the nanometer scale, accurately transferring circuit patterns from photomasks to silicon wafers becomes increasingly chall... » read more

eBeam Initiative At SPIE ALP 2026: Continuing Progress On Curvilinear, EUV, And Data Challenges


The eBeam Initiative’s annual lunch at SPIE Advanced Lithography and Patterning has long served as a focal point for eBeam technology education for the industry. This year marked our 17th gathering, with approximately 150 attendees joining us. As in past years, the value of the session was less about any single topic and more about the collective signal across different parts of the ecosystem... » read more

Research Bits: Mar. 31


2D hard mask material Researchers from Penn State University and University of Chemistry and Technology Prague propose using the 2D material chromium oxychloride (CrOCl) as a hard mask, because its layered structure is resistant to plasma etching and enables it to be an effective mask at smaller thicknesses. “This 2D material is like lasagna. It’s a layer-by-layer structure,” said Zih... » read more

Exploring The Frontiers Of Lithography And Patterning: Highlights From SPIE Advanced Lithography + Patterning 2026


Leading‑edge system-on-chip (SoC) designs at deep submicron nodes are stretching lithography and patterning capabilities across the entire manufacturing flow. Extreme ultraviolet (EUV) lithography has become central to printing advanced features, using high‑power pulsed lasers to generate a plasma light source and reflective optics to project mask patterns onto the wafer. As error budgets t... » read more

Expert Panel Sees History Of Continuous Photomask Innovations As Key To The Future


The eBeam Initiative conducted its 14th annual eBeam Initiative Luminaries survey in July and reported the results on September 23, 2025 to more than 200 attendees at its annual meeting during the BACUS SPIE Photomask Technology conference. Industry luminaries representing 51 companies from across the semiconductor ecosystem—including photomasks, electronic design automation (EDA), chip desig... » read more

Charting The Frontiers Of Photomask Technology And Extreme Ultraviolet Lithography


The enormous computing demands of AI and high-performance computing (HPC) applications are putting intense pressure on every aspect of chip development. Challenges arise during architecture, design, and verification, persist through the manufacturing process, and extend to post-silicon lifecycle management as chips are deployed in the field. Lithography, the fabrication step of shining light... » read more

GPU Acceleration Of Rigorous Lithography Simulations


Producing modern semiconductor devices is an immensely challenging process. Successful execution entails advanced process nodes, novel device architectures, new materials, and many fabrication steps. One especially challenging area is lithography, in which light is sent through a photomask, passes through a projection system of lenses and mirrors, and strikes the substrate to create the device ... » read more

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