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Circuit knitting Based On Quasiprobability Simulation


New paper "Circuit knitting with classical communication, " from researchers at ETH Zurich and IBM Quantum. Abstract: "The scarcity of qubits is a major obstacle to the practical usage of quantum computers in the near future. To circumvent this problem, various circuit knitting techniques have been developed to partition large quantum circuits into subcircuits that fit on smaller devices,... » read more

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards


By Martin James, Gary Dick, and Arif Khan, Cadence with Suhas Pai and Brian Rea, Intel The Compute Express Link™ (CXL™) 2.0 specification, released in 2020, accompanies the latest PCI Express (PCIe) 5.0 specification to provide a path to high-bandwidth, cache-coherent, low-latency transport for many high-bandwidth applications such as artificial intelligence, machine learning, ... » read more

EDA On Cloud Presents Unique Challenges


Discussions about cloud-based EDA tools are heating up for both hardware and software engineering projects, opening the door to vast compute resources that can be scaled up and down as needed. Still, not everyone is on board with this shift, and even companies that use the cloud don't necessarily want to use it for every aspect of chip design. But the number of cloud-based EDA tools is growi... » read more

Why Comparing Processors Is So Difficult


Every new processor claims to be the fastest, the cheapest, or the most power frugal, but how those claims are measured and the supporting information can range from very useful to irrelevant. The chip industry is struggling far more than in the past to provide informative metrics. Twenty years ago, it was relatively easy to measure processor performance. It was a combination of the rate at ... » read more

Comparing Formal And Simulation Code Coverage


There is a difference in semantics between code coverage generated from a simulator engine and code coverage generated from a formal engine. This paper seeks to raise the awareness of verification engineers on how best to make use of the code coverage data generated by different verification engines. The paper lays out the reasons for using code coverage and describes how simulation code covera... » read more

Data Security Challenges In Automotive


Automakers are scrambling to prevent security breaches and data hacks in new vehicles while simultaneously adding new and increasingly autonomous features into vehicles that can open the door to new vulnerabilities. These two goals are often at odds. As with security in any complex system, nothing is ever completely secure. But even getting a handle on this multilayered issue is a challenge.... » read more

Comparing And Spotting The Difference Between Two Simulations


Comparing is a basic skill we all use in our daily lives in order to understand reality and analyze situations. When it comes to chip verification, the fundamental task of checking also involves comparing because checking is always "checking vs. something" — the ASIC specification and/or a model. In practice, when we encounter a failing test, oftentimes we have a comparable passing tes... » read more

Radar Systems


Combined with advances in phased-array antennas and integration technologies, radars are moving beyond military/aerospace markets to address a host of commercial applications. This white paper showcases how the Cadence AWR Design Environment platform provides designers with a host of modeling and simulation technologies needed to meet the challenges of all types of radar system design. Click h... » read more

Reliability Concerns Shift Left Into Chip Design


Demand for lower defect rates and higher yields is increasing, in part because chips are now being used for safety- and mission-critical applications, and in part because it's a way of offsetting rising design and manufacturing costs. What's changed is the new emphasis on solving these problems in the initial design. In the past, defectivity and yield were considered problems for the fab. Re... » read more

Challenges With Stacking Memory On Logic


Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

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