SMART Fracture


With the new unstructured mesh method (UMM) in ANSYS Mechanical, engineers can reduce preprocessing time by employing UMM’s automatically generated all-tetrahedral (tet) mesh for crack fronts, while achieving the same high-fidelity results as a simulation run with the ideal hex mesh configuration. Meshing time has been reduced from up to several days to a few minutes. Using UMM, ANSYS has ... » read more

Autonomous Vehicle Design Begins To Change Direction


Tools that are commonly used in semiconductor design are starting to be applied at the system level for assisted and autonomous vehicles, setting the stage for more complex simulated scenarios and electronic system design. Simulation is well understood for designing automotive ICs, but now it also is being used to design vehicle architectures and sensors, as well as for sensor miniaturizatio... » read more

Mitigating Risk Through Verification


Verification is all about mitigating risk, and one of the growing issues alongside of increasing complexity and new architectures is coverage. The whole notion of coverage is making sure a chip will work as designed. That requires determining the effectiveness of the simulation tests that stimulate it, and its effectiveness in terms of activating structures of functional behavior and design.... » read more

Formal Signoff


Xiaolin Chen, senior AE at Synopsys, looks at what’s good enough coverage, what makes one assertion better than another, and where the potential holes are in verification. https://youtu.be/nBtKE0gDHBU » read more

Simplifying Mixed-Signal Verification With The Symphony Platform


As complexity of mixed-signal SoCs grows, verification engineers cannot rely on the “divide and conquer” approach of verifying digital and analog blocks individually and then stitching them together for full-chip verification. Verification teams need to run an increasing number of mixed-signal simulations at the top level as well as at the subsystem to make sure there are no functional erro... » read more

Formal Datapath Verification


J.T. Longino, formal verification application engineer at Synopsys, drills down into how to achieve confidence in datapath designs by applying formal solvers and methods to data transformation areas of a design rather than the control path areas. https://youtu.be/n1zO3GxEZVI     See other tech talk videos here. » read more

How to Design, Optimize and Validate Safe Laser Headlamps Through Virtual Experimentation


Today, car manufacturers and their suppliers are facing a real challenge: designing attractive laser headlamps that will illuminate the road without blinding drivers and pedestrians. Validating the safety of these headlight systems using physical prototypes would require millions of miles of night-driving testing and cost-prohibitive investment. Simulation is the only option for adequately a... » read more

Integrating Results And Coverage From Simulation And Formal


Not so long ago, formal verification was considered an exotic technology used only by specialists for specific verification challenges such as cache coherency. As chips have grown ceaselessly in size and complexity, the traditional verification method of simulation could not keep pace. The task of generating and running enough tests consumed enormous resources in terms of engineers, simulation ... » read more

Re-using Common Simulation Set-Up Processes To Speed Regression


Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And thousands of tests are run in the verification of a design. This set up phase could be either executing the exact same sequence of simulation steps, or programming the design to reach the same i... » read more

Lab-To-Fab Testing


Test equipment vendors are working on integrating testing and simulation in the lab with testing done later in the fab, setting the stage for what potentially could be the most significant change in semiconductor test in years. If they are successful, this could greatly simplify design for test, which has become increasingly difficult as chips get more complex, denser, and as more heterogene... » read more

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