tag: OPC

Accelerating Computational Lithography With GPU Rasterization
By Loay Hegazy - 02 Jul, 2026 - Comments: 0

By Loay Hegazy, Mohamed Taher, and Sherif Hammouda Semiconductor manufacturing at advanced nodes has become a race against physics. Even as feature sizes shrink, the tools that design and validate these circuits must operate with precision and speed. We show in a recent research paper that one part of the post-tapeout flow, rasterization, can be significantly sped up by deploying GPUs for ma... » read more

Optimizing Curvilinear OPC: Vector- Based Site and Anchor Decoupling
By Siemens EDA - 24 Jun, 2026 - Comments: 0

As semiconductor technology advances to sub-5 nm nodes, curvilinear mask features are essential for pattern fidelity but challenge traditional OPC methods. Siemens introduces an advanced vector-based site and anchor decoupling framework that independently and dynamically controls OPC fragmentation and optimization. This innovation significantly boosts process window robustness, speeds up mask r... » read more

Mask Economics Shape High-NA EUV Adoption
By Gregory Haley - 22 Jun, 2026 - Comments: 1

Key Takeaways: Mask costs are not stopping leading-edge scaling, but they increasingly influence design, node, and process choices. High-NA EUV will tighten requirements for CD, EPE, local CDU, mask 3D modeling, stitching, and materials. Reduced depth of focus in High-NA EUV will drive new resist, etch, film, and absorber approaches. Experts at the table: Semiconductor Engin... » read more

Curvilinear Masks Push The Limits Of Inspection And Metrology
By Gregory Haley - 27 May, 2026 - Comments: 0

Key Takeaways: Curvilinear masks require native data flows across design, mask data prep, writing, inspection, and metrology. Inspection is shifting from finding all defects to identifying which mask variations actually print on wafer. High-NA EUV will intensify inspection challenges, particularly for small printable defects and actinic contrast limits. Experts at the table... » read more

Mask Technology Faces A New Set Of Challenges
By Gregory Haley - 21 May, 2026 - Comments: 0

Key Takeaways: Mask inspection and repair remain the critical bottleneck, even as multi-beam writers have reduced mask-writing constraints. Curvilinear masks are becoming viable for critical layers, but qualification, metrology, and inspection standards still lag production needs. Scaling curvilinear requires curvilinear-native data flows, model-based checks, GPU/HPC compute, and les... » read more

Scalable Photomask Optimization With Morphological Learning (SUNY Buffalo, VU, IBM)
By Technical Paper Link - 18 May, 2026 - Comments: 0

A new technical paper, "MorphOPC: Advancing Mask Optimization with Multi-scale Hierarchical Morphological Learning," was published by researchers at University at Buffalo, Villanova University, and IBM T. J. Watson Research Center. Abstract "As feature sizes shrink to the nanometer scale, accurately transferring circuit patterns from photomasks to silicon wafers becomes increasingly chall... » read more

Exploring The Frontiers Of Lithography And Patterning: Highlights From SPIE Advanced Lithography + Patterning 2026
By Travis Brist - 19 Mar, 2026 - Comments: 0

Leading‑edge system-on-chip (SoC) designs at deep submicron nodes are stretching lithography and patterning capabilities across the entire manufacturing flow. Extreme ultraviolet (EUV) lithography has become central to printing advanced features, using high‑power pulsed lasers to generate a plasma light source and reflective optics to project mask patterns onto the wafer. As error budgets t... » read more

Faster Mask Synthesis With GPUs
By Travis Brist - 18 Dec, 2025 - Comments: 0

Design teams face rising pressure to deliver larger chips with higher transistor densities on tighter schedules using advanced node processing. The computing demands of modern applications, especially those making heavy use of AI, are extending pressure beyond design to every step of the development flow, including manufacturing, where photolithography and mask synthesis must keep pace. This po... » read more

Charting The Frontiers Of Photomask Technology And Extreme Ultraviolet Lithography
By Travis Brist - 23 Oct, 2025 - Comments: 0

The enormous computing demands of AI and high-performance computing (HPC) applications are putting intense pressure on every aspect of chip development. Challenges arise during architecture, design, and verification, persist through the manufacturing process, and extend to post-silicon lifecycle management as chips are deployed in the field. Lithography, the fabrication step of shining light... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs
By Laura Peters - 15 Oct, 2024 - Comments: 0

Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

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