193i Lithography Takes Center Stage…Again

High-NA EUV is still in the works, but more chips/chiplets will be developed using older, less-expensive equipment.


Cutting-edge lithography to create smaller features increasingly is being supplemented by improvements in lithography for mature process nodes, both of which are required as SoCs and complex chips are decomposed and integrated into advanced packages.

Until the 7nm era, the primary goal of leading-edge chipmakers was to pack everything onto a single system-on-chip (SoC) using the same process technology. Since then, those chips increasingly are being separated into individual chips, chiplets, or modules, allowing chipmakers to add many new features that previously were sidelined due to the limited area of a EUV reticle (858mm²). This decomposition also allows chipmakers to keep analog features such as RF and power in whatever process technology makes the most sense, without the expense and headaches of creating mostly digital functionality with an analog component (often called big D/small A).

Intel Foundry Services, Samsung Foundry, and TSMC continue to back ASML’s development of even more advanced lithography equipment — with a reported price tag of $340 million for every new high-NA EUV scanner, and possibly even more if hyper-NA EUV actually appears at some future node. But the more immediate concern is how to extend 193nm immersion technology, which accounts for an estimated 80% of all semiconductors, according to GlobalFoundries. Those chips will be needed in everything from electrified vehicles and charging stations to medical devices, and even the less critical functions in servers.

“You’re going to optimize whatever lithographic technology you have,” said Harry Levinson, principal lithographer at HJL Lithography. “There are two things in play right now, and they’re related. One is inverse lithography technology, which allows you to maximize your process window, so you can squeeze just a little bit more out of any given wavelength that you have in any given optical system. That’s been held up in the past by the speed at which the computations can be done. It’s been too slow to be applied to a full chip and almost impractical even for small pieces of the circuit. But it’s speeding up, and people have been applying it to increasingly larger sections of their layouts. We’re poised to be able to apply it to full chips. At least one company, Micron, presented a paper saying that’s what they’re doing.”

Related to that is the ability to print curvy features rather than rectilinear ones. “You get better process windows with curvy features than rectilinear approximations,” Levinson said. “There are a number of obstacles, and people are working on those. But using curvy features was one of the biggest topics of the very recent Photomask Japan [2023] conference, and it certainly was a topic at the [SPIE] Advanced Lithography and Patterning in February.”

While there will be continued demand to shrink some digital logic into the sub-1nm range using high-NA EUV, there is a simultaneous explosion of growth in the 193nm deep ultraviolet (DUV) range, which is where many of the chiplets and analog functions are being developed.

A good measure of 193nm activity is 200mm wafer capacity. Clark Tseng, senior director of the SEMI Market Intelligence Team, estimates that worldwide capacity will grow from 6.9 million wafers per month in 2023 to 7.5 million in 2026, which is an 8.7% increase. He noted that, at least for the time being, legacy processes in 200mm will have a limited role in chiplet architectures.

Chiplets use today is limited to the biggest chipmakers, and virtually all of those chiplets are internally developed. But that will change over time as chiplets are commercialized, and demand for DUV capacity likely will grow as a result.

“There’s a strong desire at a very high level to be able to mix and match functionality and not have to redesign every custom die for every market slice,” said Mike Kelly, vice president of advanced packaging development and technology integration at Amkor Technology. “It’s becoming feasible and cost-effective, and you’re seeing the system architects really starting to take advantage of it. As we show more and more of this is ready for prime time, these architects are going to go, ‘Okay, great, I can do that. It’s relatively risk-free. Now, how about this?'”

There are many ways to design systems-on-chip, or systems comprised of chips or chiplets in an advanced package. Unless form factor dictates the need to cram everything into the smallest area possible, in many cases a collection of chips or chiplets developed at mature nodes with DUV and packaged using high-speed interfaces may be sufficient and much less expensive.

“Our 22FDX is the epiphany of that,” said Gregg Bartlett, CTO at GlobalFoundries, in an interview last year. “It’s like a Swiss Army knife. You can do ultra-low leakage. You can do ultra-low power. You can do millimeter wave. You can put high voltage on it because you can build devices in bulk with SOI devices on there, and certainly you can speed time-to-market with whatever the customer wants.”

The number of options is growing, from different materials and architectures, to different ways of using existing technology. Given the industry’s familiarity with double patterning, much of that caused by repeated delays in bringing EUV to market, 193nm lithography is widely proven down to 14nm.

“While EUV fabs have all of their top talent working on EUV, most fabs in general don’t have — nor plan to have — EUV,” says Aki Fujimura, CEO of D2S. “So, there’s a lot of top talent in the industry who have the time to work on non-EUV leading edge and continue to scale down, particularly by using photomasks with combinations of reticle enhancement techniques (RETs), including curvilinear features.”

The three top foundries continue to use both DUV and EUV, but there is a significant opportunity for everyone else to capitalize on existing investments in 193nm processes. At the leading edge of 193nm, however, fabs face many challenges in achieving sub-nanometer alignment accuracy, maximizing equipment utilization, and improving overall yields.

“There’s an awful lot of money to be made in semiconductors away from that bleeding edge, and we tend to sort of neglect that to a certain extent,” says John Sturtevant, senior director of product development at Siemens EDA. “A very small number of companies are focusing on EUV and eventually high-NA EUV, but there are many companies that have made the investment in 193nm and probably made an investment in immersion a few years later. Those companies have a lot of capacity, and the question is how to enable them to push those resolutions as far as they can with the highest yield.

The Rayleigh resolution criteria:
At its core, the resolution of any lithography process is bound by the Rayleigh resolution criteria. This limitation is determined by the wavelength, numerical aperture, and a factor known as k1. With wavelength and numerical aperture currently at their limits, k1 is the area where many innovative solutions are applied to increase resolution, reduce pitch, and achieve nodes as low as 20nm. These smaller critical dimensions can be achieved by using a combination of smaller light wavelength and larger lens numerical aperture (NA), while pushing k1 as close as possible to the 0.25 physical limit of lithography.

CD = k1 · λ/NA

In the Rayleigh equation, CD is the smallest possible feature size, and λ is the wavelength of light and NA is the numerical aperture of the lens on the scanner used. NA defines how much light gets through, and k1 is a coefficient made up of multiple possible processes.

Immersion lithography
Immersion lithography is a technique that uses a liquid medium, typically water, between the projection lens and the wafer to increase the numerical aperture (NA), improving the resolution of the lithographic process. The liquid medium also increases the depth of focus and helps reduce the impact of topographic variations on the wafer’s surface, allowing for greater process latitude and improved yield. The first practical implementation of immersion lithography in the semiconductor industry occurred around 2006 as a solution to push the limits of optical lithography beyond what was achievable with dry lithography in the wake of multiple delays in the rollout of EUV.

Liquid immersion introduced new challenges in terms of fluid handling and contamination control. Specialized immersion systems were developed to handle, dispense, and effectively recover the immersion fluid. Maintaining the cleanliness of the immersion fluid is crucial to avoid defects and yield issues during the lithographic process.

Immersion lithography also imposes additional constraints on mask design due to the presence of the immersion fluid. The interaction between the immersion fluid and the mask can cause lensing effects and alter the image quality. Designing masks that can withstand the fluid interactions and ensure accurate patterning has been a significant challenge.

Multi-patterning is a technique that involves breaking down complex patterns into multiple simpler patterns, which are then individually exposed on the wafer and combined to form the desired pattern. The technique originally was explored in the early 1990s as complementary phase shift mask technology, but its practicality in manufacturing was considered questionable. However, as delays in EUV technology kept pushing that process further out, the industry eventually was forced to embrace multi-patterning techniques in the mid-2000s to enable the continuation of Moore’s Law and facilitate the transition to advanced process nodes.

“Since there’s no getting around the wavelength limits or the numerical aperture, we see more and more companies making the investment in double patterning to reach lower nodes, from 45nm to 28nm to 22nm,” says Sturtevant. “Double patterning, and by extension multi-patterning, is the ultimate cheat for reducing the Rayleigh Criteria’s k1 factor because you literally cut it in half as soon as you do double patterning.”

Over the past decade, extensive work has been done to develop efficient algorithms for decomposing input designs into two, three, or even four masks. Memory manufacturers have particularly favored self-aligned double patterning or self-aligned quadruple patterning, taking advantage of the ingenuity of the process, including deposition and etching techniques.

“The minimum resolution of current immersion 193 scanners, with 1.35NA, is 80nm, with double patterning this goes down to 40nm pitch (20nm lines x 20 nm spaces),” says Phillipe Leray, advanced patterning director at imec. “By applying pitch division by four, one can get down to 20 to 21nm pitch ground rules. Control of critical dimension uniformity is limited by the pitch ‘walking’ phenomena of the core structure, and edge placement error of the block and via layers are the key limitation, but the industry has built strong experience. The level of control reached today is mature and very competitive.”

Techniques such as self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and self-aligned lithography-etching (SALELE) are all multi-patterning solutions. These processes rely on spacer deposition technology, primarily atomic layer deposition (ALD), which enables control of the resulting critical dimension (CD).

Rethinking the mask
Curvilinear masking presents an intriguing opportunity for improving sub-resolution assist features (SRAFs) and expanding the process window. Although SRAF technology has been in use since the era of I-line lithography, advancements in depth of focus have highlighted the benefits of moving from rectilinear (Manhattan) SRAFs to curvilinear SRAFs.

“Curvy masks provide superior wafer results so long as masks can be written accurately and in reasonable time/cost,” says Fujimura. “Multi-beam writes any shapes in constant time given a resist and writing method. Variable-shaped-beam (VSB) write times are a function of shot count, but mask-wafer co-optimization (MWCO) combines overlapping VSB shots and produces superior wafer quality with less shots by evaluating shot position based on mask-wafer double simulation. Our most recent results show superior shot count compared to traditional (non-curvy) optical proximity correction (OPC) with far superior wafer process windows.”

The transition to curvilinear SRAFs can yield a process window enhancement of about 20%. While it is not a necessity for technologies at 193nm and above, it has proven valuable for smaller nodes. The availability of multibeam mask writers has facilitated the adoption of curvilinear masking, breaking the long-standing paradigm of mask cost tied to shot count. While there is increased cost associated with curvilinear masking, they are relatively small compared to the investment in EUV lithography.

“At the same time that EUV started entering high-volume manufacturing (HVM), the industry began to adopt multi-beam mask writers,” says Fujimura. “Practically all EUV masks are written with multi-beam mask writers now, but the prior-generation variable-shaped-beam mask writers still dominate the mask writers available in mask shops today.”

Fig. 1: The 2022 annual Luminaries Survey conducted by the eBeam Initiative identified the challenges to manufacturing curvilinear masks. Mask shop software infrastructure was the highest concern. Source: eBeam Initiative

But this isn’t always as simple as it sounds. EDA tools are excellent at automating rectilinear shapes, but they are far less so when it comes to curves. “It would be great if they actually start to incorporate curvy features in the design,” said HJL’s Levinson. “That’s the next step. There’s a whole bunch of things there, like how do you do place-and-route? And once you do that, you’ve got to deal with parasitic extractions.”

OLE for process control
A crucial factor in achieving higher yields from techniques that extend 193nm technology is OLE for Process Control (OPC). Semiconductor fabs use many pieces of equipment from different manufacturers, each with its own communication protocols. OPC acts as a framework that enables seamless communication and integration between various software applications, equipment, and control systems involved in the fabrication process.

OPC provides a standardized interface for integrating and optimizing equipment performance. By implementing OPC servers on the equipment and OPC clients in control systems, manufacturers can gather real-time equipment data, perform equipment health monitoring, and implement predictive maintenance strategies. This integration and optimization contribute to improved yield by minimizing equipment downtime, reducing variability, and ensuring efficient process control.

OPC enables real-time process monitoring and control, allowing manufacturers to closely monitor critical parameters and variables throughout the manufacturing process. In advanced nodes of 193nm technology, where precise control is essential, OPC facilitates the collection and analysis of data from multiple sources, such as sensors, actuators, and metrology equipment. This real-time monitoring helps identify process deviations and enables quick corrective actions, ultimately enhancing yield and reducing manufacturing defects.

As the industry progresses in pushing the leading edge of 193nm lithography, OPC has become a standard practice. Companies at the forefront of technology have already adopted OPC to overcome the challenges associated with smaller nodes and 193nm lithography.

The combination of OPC and curvilinear masking is a powerful approach to improving yield and accuracy by minimizing edge placement errors to sub-nanometer tolerances. The accuracy of OPC simulations is complemented by the need for in-circuit verification, which also drives the adoption of advanced metrology techniques.

Machine learning
Semiconductor manufacturers are embracing the power of machine learning (ML) and deep learning (DL), both subsets of artificial intelligence (AI), to address complex challenges and unlock new opportunities in their 193nm processes. ML algorithms analyze large volumes of data generated during the lithography process, enabling faster and more accurate identification of critical features and potential issues.

“There’s no stopping the AI train,” says Sturtevant. “But fabs are still reluctant about committing these multimillion-dollar mask sets to AI because, what if in some design on some level, or somewhere in the circuitry, it does something weird? So, the verdict is still out on that, but there is great opportunity for machine learning technologies for looking for patterning hotspots. If you can do that with improved efficacy through analyses, it’s a multimillion-dollar savings proposition to the fab that otherwise has to use lots of things like bright field inspection metrology to find these things during the process.”

Pattern recognition algorithms trained on extensive datasets can quickly identify patterns and optimize exposure parameters, leading to higher resolution and better critical dimension (CD) control. Hotspot detection using ML algorithms helps identify areas prone to lithography process failures, allowing for proactive measures to mitigate these issues. Moreover, ML-powered defect inspection systems provide real-time analysis, reducing false positives and improving overall yield.

“Supporting ILT/OPC is one of the most prominent ways deep learning is used to help with semiconductor manufacturing, but other areas like Automatic Defect Classification (ADC), machine maintenance prediction or fault identification are also ripe for deep learning contributions,” says Fujimura.

By analyzing complex interactions between process inputs and outputs, ML models can identify optimal process conditions that maximize yield and minimize defects. This optimization leads to improved process efficiency and product quality, especially as the industry explores new avenues such as chiplets and 3D packaging.

ML also plays a crucial role in data processing for various lithography applications beyond pattern recognition and defect detection. For example, ML can be used for defect classification, e-beam image denoising, and electrical performance prediction.

Other options
Lithography isn’t the only way to create a chip. Most litho is used for etching lines into silicon or some other material. Some structures also can be grown uniformly using directed self-assembly, although currently it’s being used more to fix patterns than to print them on a mask or chip.

“There are several different ways to use DSA,” said David Fried, vice president of computational products at Lam Research. “There are pattern-healing applications, where you still complete a full pattern module, but then you use DSA to heal some of the pattern non-uniformities, such as missing hole defects or line-edge roughness smoothing. I’ve seen great demonstrations of DSA in these types of process flows, and we are going to see DSA used in this way relatively soon. DSA doesn’t replace the deposition and patterning flows, it just enhances them. Pattern multiplication is an interesting aspect of DSA, where you pattern a single line and you let the DSA process produce a frequency multiplied version of that. That’s quite tricky, though. The industry has gotten so good at spacer-assisted multi-patterning that DSA is going to have a challenging time replacing-spacer assisted frequency multiplication. In addition, actual pattern growth out of DSA is probably a long way off. These are three different potential insertion points for DSA. The first will probably happen relatively soon. The second one is going to struggle because the industry has gotten incredibly good at spacer-assisted multi-patterning. I’m not sure if or when that third use case will happen.”

Looking ahead
Extending 193nm processes to smaller nodes will continue to play a vital role in semiconductor manufacturing. Despite the challenges and limitations, the industry has made significant progress in developing techniques such as multi-patterning to achieve pitch scaling. Ongoing advancements in spacer deposition technology and lithography processes will further refine the control of CDU and edge placement, enabling even smaller pitch ground rules.

Additionally, the integration of chiplets and 3D processes/packaging is introducing new opportunities and complexities. Collaborative efforts between chip designers, lithography experts, and packaging engineers will be crucial to ensure efficient integration while maintaining high reliability and performance.

The utilization of ML algorithms for data processing and optimization will enhance the overall efficiency and effectiveness of lithography processes. As the semiconductor industry evolves, it is poised to witness transformative changes driven by ML, advanced lithography techniques, and margin optimization strategies. The increasing complexity of designs, the adoption of new materials, and the demand for higher performance devices necessitate its adoption.

“If you look at the roadmap out for the next 8 to 10 years, we’re finally going to see an end to classical Moore’s Law scaling, because the fact is, nobody’s working on a wavelength below 13.5 nanometers, and nobody’s really working on a numerical aperture above 0.55,” says Sturtevant. “We’re not going to have smaller pitch after about the 1.2nm, or 12 angstrom, node. So, then the question is, how are we going to get innovation? I think multi-patterning, curvilinear masking, machine learning and 3D integration are the prime things that people are pointing to for more cost-effective manufacturing that gets more function into each package. This will allow most manufacturers to not have to invest in the next generation of photolithography equipment. By adopting these approaches, they can stay at 193nm and make whatever kind of devices they want more and more powerful and keep their costs low.”

Extending 193nm processes to smaller nodes presents challenges and opportunities in the semiconductor industry. Multi-patterning and spacer deposition technology have shown promise in achieving pitch scaling, despite difficulties in controlling CDU and edge placement. And ML technologies facilitate data processing for lithography applications, optimizing decision-making and process parameters.

Still, greater collaboration between experts in chip design, lithography, packaging, and AI/ML will be needed for success at smaller nodes and for innovative chip architectures to ensure 193nm lithography remains compatible with emerging trends.

—Ed Sperling contributed to this report.

Leave a Reply

(Note: This name will be displayed publicly)