tag: directed self assembly

Block Copolymer and Sub-10nm Line Patterns By Directed Self-Assembly (Tokyo Tech)
By Technical Paper Link - 11 Sep, 2024 - Comments: 0

A technical paper titled "Chemically tailored block copolymers for highly reliable sub-10-nm patterns by directed self-assembly" was published by researchers at Tokyo Institute of Technology and Tokyo Ohka Kogyo Co. Abstract "While block copolymer (BCP) lithography is theoretically capable of printing features smaller than 10 nm, developing practical BCPs for this purpose remains challeng... » read more

Week In Review: Semiconductor Manufacturing, Test
By Gregory Haley - 18 Aug, 2023 - Comments: 0

Intel dropped out of a $5.4 billion deal to purchase Tower Semiconductor in Israel. Intel cited the inability to obtain regulatory approval in a timely manner as the reason for ending the deal signed in February. Intel will pay a $353 million termination fee to Tower. The silicon wafer supply has moved back into positive territory for 2023 thanks to a 7% decline in wafer shipments combined w... » read more

Directed Self-Assembly Finds Its Footing
By Gregory Haley - 17 Aug, 2023 - Comments: 0

Ten years ago, when the industry was struggling to deliver EUV lithography, directed self-assembly (DSA) roared to the forefront of research and development for virtually every manufacturer determined to extend the limits of 193i. It was the hot topic at of the 2012 SPIE Advanced Lithography Conference, with one attendee from Applied Materials comparing its potential to disrupt the industry to ... » read more

193i Lithography Takes Center Stage…Again
By Gregory Haley - 15 Jun, 2023 - Comments: 0

Cutting-edge lithography to create smaller features increasingly is being supplemented by improvements in lithography for mature process nodes, both of which are required as SoCs and complex chips are decomposed and integrated into advanced packages. Until the 7nm era, the primary goal of leading-edge chipmakers was to pack everything onto a single system-on-chip (SoC) using the same process... » read more

Define & Grow III–V Vertical Nanowires At A High Footprint Density on a Si Platform
By Technical Paper Link - 29 Jul, 2022 - Comments: 0

New technical paper titled "Directed Self-Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All-Around Deposition" is published from researchers at Lund University in Sweden. Abstract: "Fabrication of next generation transistors calls for new technological requirements, such as reduced size and increased density of structures. Development of cost-effective proc... » read more

Lithography Options For Next-Gen Devices
By Mark LaPedus - 18 Apr, 2019 - Comments: 2

Chipmakers are ramping up extreme ultraviolet (EUV) lithography for advanced logic at 7nm and/or 5nm, but EUV isn’t the only lithographic option on the table. For some time, the industry has been working on an assortment of other next-generation lithography technologies, including a new version of EUV. Each technology is different and aimed at different applications. Some are here today, w... » read more

Single Vs. Multi-Patterning EUV
By Mark LaPedus - 25 Mar, 2019 - Comments: 5

Extreme ultraviolet (EUV) lithography finally is moving into production, but foundry customers now must decide whether to implement their designs using EUV-based single patterning at 7nm, or whether to wait and instead deploy EUV multiple patterning at 5nm. Each patterning scheme has unique challenges, making that decision more difficult than it might appear. Targeted for 7nm, single pattern... » read more

EUV Arrives, But More Issues Ahead
By Katherine Derbyshire - 21 Mar, 2019 - Comments: 5

EUV has arrived. After decades of development and billions of dollars of investment, EUV lithography is taking center stage at the world’s leading fabs. More than 20 years after ASML's extreme ultraviolet lithography research program began, and nearly a decade after its first pre-production exposure tools, the company expects to deliver 30 EUV exposure systems in 2019. That is nearly doubl... » read more

Using DSA With EUV
By Ed Sperling - 05 Nov, 2018 - Comments: 1

James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science, looks at how directed self-assembly can be used to supplement EUV at advanced nodes. https://youtu.be/PItF4egHOxc     See other tech talk videos here » read more

DSA Re-Enters Litho Picture
By Mark LaPedus - 15 Mar, 2018 - Comments: 1

By Mark LaPedus and Ed Sperling Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography. Intel continues to have a keen interest in [gettech id="31046" t_name="DSA"], while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn't like a traditional [getkc id="80" kc_name="... » read more

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