Single Vs. Multi-Patterning EUV

Why this choice isn’t as obvious as it might look.

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Extreme ultraviolet (EUV) lithography finally is moving into production, but foundry customers now must decide whether to implement their designs using EUV-based single patterning at 7nm, or whether to wait and instead deploy EUV multiple patterning at 5nm.

Each patterning scheme has unique challenges, making that decision more difficult than it might appear. Targeted for 7nm, single patterning creates patterns on devices with tight pitches using a single EUV lithographic exposure, but with today’s resists this is a relatively slow operation. It also can cause unwanted random or stochastic defects in patterns, which affect yield. In addition, companies working at the most advanced nodes are scrutinizing where to invest their development resources because 5nm processes already are well underway.

At 5nm, double patterning will be required on the critical layers even with EUV. Still, there are some important advantages in doing it this way. For example, the pitches of features can be relaxed and then processed. That, in turn, can reduce the number of defects. Moreover, many of the companies working at the leading edge are well-versed in multi-patterning. The downside is it requires more expensive steps, which further increases the already astronomical IC design costs.

In either case, EUV can have a big impact. While chipmakers have extended traditional 193nm lithography and multi-patterning to 10/7nm, it’s too difficult and expensive to push beyond that node for the most complex features without using EUV. 7nm is the crossover point, and there is still debate about which approach to use. Even where EUV is deployed, other portions of a device will be developed using traditional patterning techniques.

So far, both Samsung and TSMC are ramping EUV at 7nm. Intel also is developing EUV at its version of 7nm, which is roughly equal to Samsung’s and TSMC’s 5nm. Still, the technology is still considered relatively immature and unproven. For this and other reasons, one foundry customer, Apple, will adopt EUV at “5nm next year, not 7nm this year,” said Sebastian Hou, an analyst at CLSA. “At the end of the day, it comes down to economics. Even if EUV is technically ready but yield/performance are not there, customers have less incentive to migrate.”

All told, EUV presents a difficult transition for the IC industry, whether it’s single or multi-patterning. “Improvements in productivity are still required to make EUV single patterning cost-effective,” said Harry Levinson, principal at HJL Lithography, a consulting firm. “EUV double patterning will be a very expensive proposition.”

Is EUV really ready?
Today’s chips consist of three parts—the transistor, contacts and interconnects. The transistor resides on the bottom of the structure and serves as a switch. The interconnects, which sit on the top of the transistor, consist of tiny copper wiring schemes. A chip may have 9 to 12 copper metal layers. The transistor structure and interconnects are connected by a layer using contacts.


Fig. 1: Interconnect, contact and transistor at various nodes. Source: Applied Materials.

Until the industry reached the 28nm node, lithography was a straightforward process in devices. You put the features on one mask and then print them on the wafer using a single lithographic exposure. This is more or less a single patterning process. Starting at 20nm, the features became too dense on the mask, making it more difficult to print discernible features on the wafer.

And this is where multiple patterning fits in. In multiple patterning, the original mask shapes are relaxed and divided between two or more masks. “Each mask is then printed separately, eventually imaging the entire set of originally-drawn shapes onto the wafer,” explained David Abercrombie, DFM program director at Mentor, a Siemens Business, in a blog.

Today, chipmakers need EUV because it’s becoming more difficult to pattern the most difficult features, such as the bottom metal layers and contacts/vias, using today’s 193nm lithography and multi-patterning at advanced nodes. In the fab, the most common multi-patterning approaches are double patterning and self-aligned schemes.


Fig. 2: Self-aligned spacer avoids mask misalignment. Source: Lam Research


Fig. 3: Double patterning increases density. Source: Lam Research

For the difficult metal layers at 10nm/7nm, some are using 193nm immersion and double patterning. Double patterning, which has a minimum pitch of 38nm, uses two lithography and etch steps to define a single layer. This also is called litho-etch-litho-etch (LELE). Some use triple pattering, which requires three exposures and etch steps (LELELE).

“That’s where it starts to get very difficult. It’s based on the variability control,” said Michael Lercel, director of product marketing at ASML. “If you want 38nm by double pattering immersion, that means you are only doing lines. As soon as you want to have anything other than a grating, then you need more exposures on top of the theoretical number.”

EUV promises to solve the problem. For example, 193nm/multi-patterning requires three exposures to process the critical metal layers at 7nm. Single patterning EUV does the same job using a single exposure.

However, EUV has been more difficult to develop than expected. In EUV, a power source converts plasma into light at 13.5nm wavelengths. The light then bounces off 10 multi-layer mirrors in an EUV scanner. In addition, EUV consists of several components that must come together before chipmakers can insert it into production. These include the scanner, power source, resists and masks.

Later this year, ASML will ship a new version of its EUV scanner, dubbed the NXE:3400C. Like the current model, the new system has a 246-watt power source with 13nm resolutions. The new tool has a throughput of 170 wafers an hour (wph) with better uptime, compared to a throughput of 125 wph in the current model.

Besides the scanner, the EUV mask is also key. “Early adoption of EUV doesn’t require complex OPC (optical proximity correction) or ILT (inverse lithography technology), so that helps with data volume, the requirement for minimum features sizes on the mask, and being sufficiently inspected,” said Aki Fujimura, chief executive of D2S.

There are other aspects as well. “The EUV mask infrastructure is ready for the insertion of EUV at 7nm,” said Meng Lee, director of product marketing at Veeco. “Mask manufacturers have been working with device makers to get qualified for the next node. We anticipate changes in the mask multi-layer and absorber materials for 3nm and beyond.”

There are still gaps. For example, chipmakers want an EUV pellicle that can transmit light at 90%. However, ASML, the sole supplier of EUV pellicles, has shipped pellicles with 83% to 84% transmission rates. “The pellicle transmission has improved compared to what we talked about last year,” ASML’s Lercel said. “We are making the pellicles better and getting the transmissions up. We are also reducing the scanner defectivity.”

For now, some will not put EUV into production until the pellicle meets spec. Others will move into production without the pellicle. There also are issues with the photoresists. In EUV, the scanner generates photons, which then hit a resist and cause a reaction. The reactions might be different at each event. This can cause random or stochastic-induced defects in chips.

While the industry is trying to understand what causes these variations, it’s also developing tools to locate these defects. “Stochastic defects/failures are random in nature, requiring a high-level of inspection coverage across the wafer,” said Mark Wylie, senior director at KLA. “Inspection techniques–such as integration of design information and defect binning based on machine learning–help isolate the stochastic defects. To complement optical inspection, high density sampling with e-beam technologies, though slower, can provide additional information on the distribution of CDs.”

Single vs. multi-patterning EUV
Despite the challenges, foundries are gearing up for EUV. For example, TSMC is using 193nm/multi-patterning for 7nm, which is in production. Later this year, TSMC will deploy EUV for a second version of 7nm, at least for some layers. Next year, it will move into 5nm production, which will incorporate more EUV layers.

Meanwhile, Samsung will use EUV at 7nm and then 5nm. And Intel will insert EUV at the equivalent of 5nm for Samsung and TSMC.

At 7nm, EUV is particularly useful for single patterning of features with pitches starting at 38nm or 36nm, analysts said. Single patterning EUV also will be used for contacts/vias, which have larger pitches. But this is where the tradeoffs start. For the metal layers, 193nm/multi-patterning extends into the starting point for single patterning EUV. This means chipmakers must decide which technology, EUV or multi-patterning, makes sense for this app.

In addition, because EUV is late, the window has narrowed for single-patterning EUV at 7nm. While the starting point is 38nm/36nm, single-patterning EUV reaches its limit at 32nm to 30nm pitches. Beyond 30nm pitches, double patterning is required, which falls under the 5nm node. Double patterning EUV is impractical at 7nm.

Foundry customers can put a device into production with single patterning EUV and push it to its limits. But they must decide whether it makes sense to stay with 7nm EUV for a relatively short duration.

“There is a strong use case for single patterning EUV for contacts/holes. The use case for single patterning of lines was primarily design flexibility,” said Rich Wise, managing technical director at Lam Research. “There’s an effort to go down to 32nm pitch. But with the existing resist solutions, there is very little credible belief it will get below 30nm. So you are at a very narrow window on scaling before you have to go back to multi-patterning solutions.”

Indeed, there are some technical challenges here. With single-patterning EUV, the goal is to print features with tight pitches. This requires a robust EUV resist with the right sensitivity and dose.

“Dose is the amount of energy (per unit area) that the photoresist is subjected to upon exposure by a lithographic exposure system. For optical lithography, it is equal to the light intensity times the exposure time,” explained Chris Mack, CTO of Fractilia, on the Lithoguru Web site.

Dose plays a key role in the process. According to experts, the throughput of an EUV scanner is tied to the EUV power source of the system, which is then divided by the dose. For example, with a 30mJ/cm² dose, an EUV scanner with a 250-watt source has a throughput of 104 to 105 wafers per hour, according to ASML.

For EUV, chipmakers will use resists at various doses, roughly at 30mJ/cm², 40mJ/cm² and 80mJ/cm². A low dose is generally 30mJ/cm² or 40mJ/cm², while 80mJ/cm² is a higher dose.

In both cases, there are some challenges. “Let’s say you have single patterning EUV with a tight pitch. That requires a very high dose. As a result, you have a low throughput,” Mack said.

The good news is that the defectivity is reduced using a higher dose. With a lower dose (30mJ/cm²) you get tight pitches with poor results. “In single patterning, if you try to use a low dose, you will get defects,” he said.

With better resists, single-patterning EUV could print tight features with no defects, but these resists are still in R&D. Even with its shortcomings, some believe single patterning makes more sense than the alternative. “If I were leading an EUV program at a chip company, I would be pursuing resists to support EUV single patterning,” HJL’s Levinson said. “Doubling the dose is much better than double patterning.”

Like single-patterning EUV, double-patterning EUV is also challenging. If foundry customers move to 5nm, they will require double-patterning EUV for many features.

“We’ve always planned that it would go from single-patterning to double-patterning EUV,” ASML’s Lercel said. “People have used single-patterning immersion lithography. Then, they figured out how to do double patterning. So you have EUV single patterning. They’ll try to push it as long as possible, and then they will go to double patterning. Just like double-patterning immersion, it’s more expensive than single-patterning immersion.”

Still, double-patterning EUV is a better alternative than 193nm/multi-patterning at 5nm. “It would probably be 6, 7 or 8 immersion exposures, which is not at all workable,” Lercel said.

Double-patterning EUV involves splitting a chip pattern into two simpler masks. Each one is then printed as a separate layer, according to ASML. In the fab, it has the same basic process steps as immersion/double patterning. In double-patterning EUV, the idea is to relax the pitches of the features and use a higher dose. This involves more costly steps, but it may mitigate the defects.

For the metal layers at 5nm, the starting point for double patterning EUV is a 26nm pitch, according to IC Knowledge and TEL. The contacts and vias, which are larger, will use single patterning EUV at 5nm.

“The direction of EUV in manufacturing is going to be the relaxed pitch. The only way to get defect-free printing is to print at larger sizes than what you want to,” Fractilia’s Mack said. “It’s on the order of 40nm pitch. If you go a little bit less than 40nm pitch like 38nm, you are at the limit what you can do with SADP with 193nm immersion. If you can do it with single-patterning EUV, compared to triple patterning with 193nm, you start to get into an economic realm where it makes sense.”

Let’s say you want a 32nm pitch using double patterning EUV. “So you do it two times 64nm pitch exposures, and you interweave them. Then, to get 64nm with zero defects, you don’t need that high of dose,” said Greg McIntyre, director of advanced patterning at Imec. “You can maybe get away with resists at 30mJ/cm². So, if you go from a single 60mJ/cm² exposure to a two times 30mJ/cm², it’s the same number of photons. It’s just some additional processing.

“So, we are at a point where 7nm and the 7nm+ node is roughly around the node that will have all single-exposed solutions. Once you go beyond that, you are mostly likely to have at least three of your most aggressive metal layers as a double patterning scheme,” McIntyre said. “That doesn’t mean single patterning isn’t important. For example, your lowest metal level might be at a pitch that requires double patterning. But then, the metal layers above that, and a significant part of the cost savings, could still be done with single patterning EUV. All of this stuff we are doing with 32nm pitch or 34nm pitch or whatever it ends up being, it’s still going to be important for N5 and N3 and even beyond. You will have some layers that will be in multi-patterning, which is more expensive but higher performance.”

Regardless, there are some pros and cons with EUV double patterning. “There is interest in multi-patterning. So then, you can relax the pitch. The stochastic problems are more manageable. Because immersion has been in place for so long, the industry is very comfortable with multi-patterning. It’s not a new technology. In fact, it’s well established and customers are comfortable with it. It’s much easier, in some sense, to do multi-patterning. Your designs are already design-compliant to it,” Lam’s Wise said.

But it adds cost and complexity to the equation. “Every time you add more steps, there is more variability. There are more fab controls required. Imagine if you have a film thickness variation, that will show up as a variation in your profile. It’s more films. There is more cycle time in general. All those things add up,” Wise said.

There are other challenges. “EUV doesn’t solve the edge placement error problem. There are two issues. As you keep scaling, the budget for placement becomes smaller and smaller. So you need self-aligned schemes. The other big problem with EUV is this whole thing with stochastics. There are issues with stochastic failures. It’s stochastics, LER (line-edge roughness) and the process window between nano-bridging and opens,” said Uday Mitra, vice president of strategy for etch products at Applied Materials.

“Then effectively, the EUV pitch, which EUV could do for single patterning using 0.33 NA, is like something in the mid-30s. The net effect of this is when you go to smaller nodes, you can’t do single patterning EUV. You can’t get to let’s say pitches below 30nm. You have to use EUV double patterning. So you are limited to a very short span of single patterning EUV, then it becomes double patterning EUV,” Mitra said. “Double patterning technology has existed for a long time. It can be easily extended with EUV. The biggest challenge is cost, because EUV is still a very, very expensive process.”

Multi-patterning options
To complicate matters, there are several ways to implement multi-patterning EUV. Among them:

  • Double patterning EUV. This requires two lithography and etch steps.
  • Self-aligned double patterning (SADP) EUV. This uses one lithography step, plus deposition and etch steps.
  • Hybrid approaches.
  • EUV with directed self-assembly (DSA). DSA uses block co-polymers that self-align and create patterns.

Each scheme has its merits. “If you can do EUV with spacer-assisted patterning, where you limit the EUV use, that’s ok. But if you need double exposure EUV for a layer or triple exposure EUV for a layer, then it becomes very, very expensive,” Mitra said.

There are other ways to look at the issues. “Given metal layers at these nodes are essentially unidirectional tracks the double patterning methods used will most likely be self-aligned processes with cut mask(s) as opposed to LELE pattern splitting. EUV SADP with a single cut mask is certainly an option. But more than on cut mask (most likely selective/self-aligned cut masks) may be needed to resolve cut spacing constraints efficiently,” Mentor’s Abercrombie said.

Then, there is another way to look at this. “It depends on the customer. It might be self-aligned multi-patterning for some customers. That’s their bread-and-butter. They are very familiar with it. The designs are already compliant with it,” Lam’s Wise said. “Then, some customers in immersion are doing litho-etch-litho-etch-litho-etch for certain levels. You can do the same thing with EUV. You can do 2D designs. By using that with two passes at a relaxed pitch, your stochastics are manageable.”

Imec has developed a hybrid approach that resembles quadruple patterning EUV. “It’s using an EUV core and then doing a two-spacer process, as well as a self-aligned litho-etch-litho-etch process. This is a hybrid between SADP/LELE and a self-aligned block,” Imec’s McIntyre said. “SA/LELE, overall, gives the most flexibility with potential control of the process. We’ve shown processes in the range from 28nm pitch and starting to probe into a 16nm pitch.”

DSA with EUV is another approach. “The purpose of DSA and EUV is primarily for cost savings compared to double patterning EUV. Our approach offers a substantial savings in the cost of expensive EUV tool time per hour for exposure using multiple patterning strategies. It also offers the potential to save the cost of multiple reticles purchased based on requirements for multiple EUV exposures,” said Mary Ann Hockey, director of emerging technology at Brewer Science.

So what is the best multi-patterning solution? “A decision on ‘better’ depends on one’s metrics (tolerable level of LER, budget, etc.) and what is available in terms of resists and sources,” HJL’s Levinson said. “I have concerns with EUV double patterning. It may well not be double patterning, but triple patterning. Because of the current magnitude of edge placement errors, self-aligned techniques are required for the cut or block masks associated with line/space multiple patterning. But these approaches may require at least two cut or block masks.”

Clearly, there are no simple solutions. But one way or another, the industry needs to get started with EUV. It’s been in R&D for years with little to show for it. Just getting some chips out the door would be an accomplishment.

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2 comments

Enchuan says:

About LELE approach, if the inconsistency of misalignment(overlay) between 2 L(lithography) steps will bring some trouble to following patterning layer, which aligning to the pre-layer of LELE combination?

10957 reader says:

At the latest SPIE, paper 109570Q they discuss that 20 nm is the minimum sparse metal linewidth without stochastic defects so double patterning EUV is required at this design rule already.

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