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EUV Mask Readiness Challenges

Experts at the Table, Part 1: 250W power source appears sustainable and reliable, but defects in mask blanks, 3D mask effects and fabrication of those masks remain problematic.

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Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and photomask technologies with Emily Gallagher, principal member of the technical staff at Imec; Harry Levinson, principal at HJL Lithography; Chris Spence, vice president of advanced technology development at ASML; Banqiu Wu, senior director of process development at Applied Materials; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation.

Left to right, Harry Levinson, principal at HJL Lithography, Emily Gallagher, principal member of the technical staff at Imec; Chris Spence, vice president of advanced technology development at ASML; Banqiu Wu, senior director of process development at Applied Materials; Aki Fujimura, chief executive of D2S

SE: Chipmakers have extended traditional optical lithography far beyond what was once considered possible. Today, chipmakers are using 193nm immersion lithography and multiple patterning to print the critical features down to 10nm/7nm. What are the challenges here?

Levinson: The fundamental problem with optical lithography is that we are in the era of multiple patterning. And the only path forward is just to continue to add more and more optical steps. It’s not a controllable situation. Manufacturing cycle times become way too large. It’s always hard to say something is impossible. But some things become impractical. Where you define impracticality is always a little bit fuzzy. With 7nm foundry technology, we were sort of on the border. You could do it optically, but life is easier in a lot of ways with EUV. You can fall off the cliff going to the next node when it comes to optical lithography solutions. It’s too many masks.

Spence: As the complexity of defining each layer increases, the opportunity for yield impact—and even the ability to figure out where the yield problems are coming from—becomes much more difficult. So you not only have a longer cycle time for processing, but you have a longer cycle time for process development in the first place. Why EUV now? Finally, EUV looks like it can actually meet the throughputs. People always reckoned it could meet the overlay and CD targets, but there have been a number of breakthroughs in the source power over the last few years. It appears now that we are pretty solid at 250 watts. We have shown examples of performance quite a bit above that. If we can demonstrate over 100 wafers an hour with good uptime and reliability, which we are starting to see more and more in the field now, then this gives the big guys the confidence to say, ‘We see a trajectory now where we can start to ramp.’ Obviously, there is a long way to go to get the economies that they want for high-volume manufacturing. The power has reached a point now, as well as the reliability, where people can actually see a pathway to high-volume manufacturing.

SE: Chipmakers are expected to move into production with EUV lithography this year. An EUV scanner is a 13.5nm wavelength tool with 13nm resolutions. Is the EUV mask infrastructure ready for the production of EUV lithography?

Fujimura: EUV masks can be manufactured today with the existing infrastructure. A practical pellicle solution is still being worked on. Actinic or e-beam inspection are also still being worked on. The mask blank defect issues can be adequately addressed particularly for contact and via layers to buy time until the defect issues improve as anticipated over the next year or so. So, there’s still work to be done to fully enable the power of EUV to make sure that the mask issues are not the bottleneck in EUV lithography. The readiness of multi-beam e-beam mask writers is a big help in this. Other aspects are catching up quickly.

SE: EUV masks are different than optical masks. Today’s optical masks consist of an opaque layer of chrome on a glass substrate. In contrast, an EUV mask consists of 40 to 50 alternating layers of silicon and molybdenum on top of a substrate, resulting in a multi-layer stack that is 250nm to 350nm thick. On the stack, there is a ruthenium-based capping layer, followed by an absorber based on tantalum. What are some of the issues here?

Fig. 1. EUV mask. The absorber stack in the blank is patterned to form the mask. Source: GlobalFoundries

Gallagher: With EUV, since all materials absorb strongly, you now have to move to a reflective mask. That creates a mask blank with multi-layers. So you have multi-layers with this reflective mask. The absorber properties are very important. You want the absorber to be as thin as possible, but still provide good contrast to the reflective part of the mask. So you have absorber features and clear features, where you have removed the absorber to create the clear area. And that’s what creates your pattern. So now you have a reflective mask and it’s in vacuum, which is another big difference. Then there is a pellicle solution. There’s not an ideal HVM pellicle solution—yet. And that again is related to the fact that all materials absorb strongly in EUV. So, ASML has proposed an initial polysilicon pellicle. That works, but it has transmission and power limitations right now. Everybody is looking towards another one for HVM. There are other mask making differences. Because it’s in vacuum, you can’t use a vacuum chuck for the mask. It just wouldn’t function. So instead you have an electrostatic chuck. Now, you have a backside film in order to enable chucking of the mask. You have balances of different films that you might have not worked with before. Backside defectivity becomes an issue. It wasn’t an issue for 193nm. Also, because it’s a reflective mask, flatness is much harder. And because the powers are high, heating is much more of a problem than it used to be. So you now need a low thermal expansion material. For EUV, it’s a more expensive mask blank than you used to have.

Levinson: Basically, we’ve never really had an issue with defects in our glass. The multi-layers can have defects that will print. So we need to have extremely low defects here, and they can’t be repaired.

Gallagher: The defects can be avoided.

Levinson: Yes, but you need to have an infrastructure for very low defect blanks. There is a bottleneck in the industry here right now.

Gallagher: From discussions, it seems like this should be resolved somewhat next year, at least that’s the projection. Right now, it’s still a bottleneck, but it should get better. That’s lower defectivity EUV mask blanks at higher volumes. All the tooling is supposed to be in place next year to help close that gap.

Wu: There are other issues. Now, we are trying to reduce the mask 3D effects. We are trying to reduce the absorber stack and make it thinner and thinner. Originally, twenty years ago, we had a capping layer. We had a buffer layer. The buffer layer was mainly for the fabrication. The repair was straightforward as well as the etch and clean. But now, our industry has totally removed that buffer layer. We just combined the buffer layer and the capping layer. We have only one layer. It is 2.5nm ruthenium. We call it ruthenium, but it’s not pure ruthenium. This makes the fabrication very difficult, especially for clean and repair. For repair, we cannot use ion beam or laser. We have to use e-beam. If we assume the capping layer is perfect, it should be 2.5nm. It’s difficult to assume that it’s perfect. During the clean, the acid and chemicals can penetrate into it, and it’s easy to damage the layers. That makes the fabrication very difficult compared with optical masks.

Gallagher: There are two more big things. One of them is you have your patterned area and then you have a periphery. And you don’t want to have reflections from your periphery that get into your adjacent field when you are imaging. So you reflect light off the mask and you create different fields on the wafer. You don’t want to have crossover, so you need a border. On 193nm masks, that’s just an absorber and that’s good enough. In EUV, it’s not enough. So you have to dig this moat, basically a trench down to the quartz. And that creates some stress relaxation. It’s not a huge issue now, but it could create some issues. In addition, right now, there isn’t a manufacturing actinic inspection tool. Inspection wavelength and exposure wavelength have not always been matched. But most recently, they have at 193nm. We all became used to that, meaning that you should be able to pick up the defects that matter. With EUV, you can do certain types of inspections, but on small areas routinely. It’s in development, but there is not yet a full-field inspection for actinic available. So you are not matched, and that means you don’t know for sure if you have a printing defect or not when you finished your mask. You might have a line return, which creates all kinds of issues.

SE: What about the EUV mask itself? What can designers expect?

Fujimura: Early adoption of EUV doesn’t require complex OPC (optical proximity correction) or ILT (inverse lithography technology), so that helps with data volume, the requirement for minimum features sizes on the mask, and being sufficiently inspected.

Spence: The fabrication of the mask is very different. In terms of the resolution enhancement techniques, it’s kind of a mixture. Typically at the moment, most people are not using SRAFs (sub-resolution assist features). But let’s just back up. The ratio of the feature size to the wavelength, or Lambda over NA, tells you how hard you’re pushing the lithography in a traditional deep UV scanner. So if you do that same metric on EUV, you’re looking at an easier kind of patterning. So you don’t need to be as aggressive with my resolution enhancement techniques like illumination, source optimization or SRAF placement. Then, you look at some of the things about the asymmetry in the image. When you consider the fact the aberration levels in the systems are higher than they are in deep UV, then it turns out that you actually have to dial those resolutions enhancement techniques up a bit. So if you just use simple scaling, you would say EUV, where we are today, should be actually easier than what we are doing in deep UV. But it’s not much easier as you would think because of these issues. The imaging is asymmetric and the other things. That’s where we are today. In a typical EUV mask today, it doesn’t have SRAFs. It does have OPC. It does have source optimization because we really want to get the most image sharpness in order to reduce these stochastic effects. There is a premium of doing source-mask optimization. It is necessary. It does require quite a bit of computational lithography.

Related Stories:

EUV Pellicle, Uptime And Resist Issues Continue

What’s Missing In EUV?

EUV Mask Blank Battle Brewing

 



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