EUV Mask Blank Battle Brewing

Applied Materials circles market as demand for next-gen technology grows.


Amid the ramp of extreme ultraviolet (EUV) lithography in the market, suppliers of EUV mask blanks are expanding their production. And a new player—Applied Materials—is looking to enter the market.

AGC and Hoya, the two main suppliers of EUV mask blanks, are adding capacity for these critical components that are used for EUV photomasks. A mask blank serves as the substrate for a photomask. Meanwhile, at several recent events, Applied Materials has given presentations about its efforts and possible entry in the EUV mask blank business. Applied is developing next-generation EUV blanks, although it is still devising its strategy and hasn’t made a formal announcement in the arena.

Other dynamics are at play here. There is a potential supply shortfall in the market of low-defect EUV mask blanks—and high prices. An EUV mask blank with tighter specs can cost more than $100,000. That won’t stop chipmakers from using EUV lithography, but they do want better and cheaper blanks.

In limited production for years, an EUV mask blank is a key component used in an EUV photomask. In mask making, the process starts with the production of a mask blank or substrate. Once the blank is made by a mask blank manufacturer, it is shipped to a photomask maker and the mask is processed on the substrate.

A photomask is required to make a chip. In the design-through-manufacturing flow, a chipmaker designs an IC, which is translated from a file format and then produced into a mask. The mask is a master template for an IC design. Inside the fab, the mask is placed in a lithography scanner. Light is then projected through the mask and used to pattern images on a wafer.


Fig. 1. EUV mask. The absorber stack in the blank is patterned to form the mask. Source: GlobalFoundries

The goal is to make defect-free EUV mask blanks and photomasks, because if the blank or mask has a defect, the irregularities might get printed on the wafer. But while the industry can produce EUV mask blanks with tighter defect specs, there might be a shortfall of these products as the industry ramps up EUV lithography. “The biggest problem is the supply for low-defect blanks,” said Harry Levinson, principal at HJL Lithography, a consulting firm.

EUV mask blank suppliers, meanwhile, are responding to the challenges. “We are currently in production and have a roadmap for both defect reduction and spec improvement,” said Geoff Akiki, president of Hoya Blanks, part of Hoya. “To meet this demand ramp, Hoya has invested heavily in engineering resources and capital for capacity expansion.”

Applied Materials, the apparent newcomer in the business, also is investing, but it’s too soon to tell if it will alter the landscape. Applied hopes to leverage its equipment expertise to get a foothold in the market.

“We can imagine that a lot of materials engineering will be coming in the future for next-generation EUV mask blanks,” said Vibhu Jindal, manager of new markets and alliances at Applied Materials, in a recent presentation. “We are leveraging on the existing technologies that we have, whether it’s in clean, deposition, planarization and all of this equipment. We will actually innovate some of this custom development for next-generation EUV mask blanks.”

All told, the EUV mask blank business is challenging with a limited customer base. To help the industry gain some insights, Semiconductor Engineering has taken a look at the business.

Why EUV?
EUV lithography—a next-generation technology that patterns tiny features on a chip—is moving into production after years of delays. In an EUV scanner, a power source converts plasma into light at 13.5nm wavelengths, enabling the system to print fine features.

Chipmakers need EUV because it’s becoming more difficult to pattern the tiny features using today’s 193nm immersion lithography and multiple patterning. Multi-patterning uses various steps to reduce the feature sizes of a structure, but it also increases the complexity of the process.

EUV promises to simplify the process. “EUV lithography offers a desired path that allows for direct print of line and space at 36nm pitch and below and effectively addresses issues like cycle time, intra-level overlay and mask count costs associated with multi-patterning,” said Sophie Thibaut, senior etch process development engineer at TEL, in a recent paper.

Meanwhile, in a major milestone, Samsung became the industry’s first chipmaker to put EUV into production. EUV is being used for 7nm.

In contrast, TSMC earlier this year moved into production at 7nm using 193nm immersion and multi-patterning. The foundry plans to insert EUV for its second version of 7nm, which is slated for the second quarter of 2019.

Intel also plans to use EUV at some point in the future. All chipmakers are using ASML’s EUV scanner, the NXE:3400B. With a 13nm resolution, the system is equipped with a 246-watt EUV power source, enabling a throughput of 125 wafers per hour (wph).

The complexity of EUV has made it more difficult to put into production than previously thought, and it won’t be a smooth transition as EUV moves from R&D into the fab. For example, today’s 193nm scanners can run non-stop at 250 wph. However, EUV uptimes hover around 70% to 80%, meaning the system is prone to work-flow stoppages.

Initially, EUV will process a few layers at 7nm and eventually 5nm. “The use of EUV in production will most likely be a combination with multi-patterning and immersion,” said Rich Wise, managing technical director at Lam Research. “For applications like dense random vias, the use case for EUV remains strong, as the overlay and cycle time penalty for many passes of immersion lithography becomes problematic. For regular line/space patterns, these can be made using multi-patterning either with EUV at a more relaxed pitch or continued use of immersion. Other patterns fall somewhere in-between and require a careful consideration of the tradeoffs.”

Nonetheless, EUV has momentum. In one metric, EUV mask shipments are expected to increase by twofold, from 1,041 in 2017 to 2,185 in 2018, according to a survey from the eBeam Initiative. That’s a tiny percentage of overall mask shipments, as 587,233 photomasks will be delivered in 2018, up by 27% over last year, according to survey.

“EUV masks went up 2X, which is expected. That’s a good thing. But the numbers are insignificant compared to the overall masks that are reported.  But taken by itself, a 2X increase is a strong indication that the industry is getting ready for EUV,” said Aki Fujimura, chief executive of D2S.

Mask blank challenges
Besides the scanner, other key parts to EUV are the photoresists and photomasks. Resists are polymers used to create patterns.

The photomask starts off with the production of a mask blank. For years, mask blank vendors have been making blanks for today’s optical lithographic systems. In optical, the mask blank consists of an opaque layer of chrome on a glass substrate.

Fig. 2:  Fabrication of EUV mask. Source: Sematech

In contrast, an EUV mask blank consists of a substrate based on a low thermal expansion material. In the flow, the substrate is developed, polished and cleaned.

Then, a deposition tool deposits 40 to 50 alternating layers of silicon and molybdenum on top of a substrate, resulting in a multilayer stack that is 250nm to 350nm thick. On the stack, a tool deposits a ruthenium-based capping layer, followed by an absorber based on a tantalum material.

Making an EUV blank is challenging. “We have made many advances, which have given us leadership. But there are always more challenges ahead and, of course, the competition never sleeps,” Hoya’s Akiki said. “Control of defects is one of the key items in ramping up any technology and EUV blanks are especially sensitive. The situation presently is a combination of technical challenges and long tool availability lead times, coupled with a rapid increase in demands from customers.”

In the flow, the EUV mask blank production process can create defects, such as particulates, pits and bumps in the blank. Blank vendors have reduced the defect numbers to single-digit figures, down from hundreds several years ago. But any defects on the blanks are problematic.

“Defectivity challenges begin with the EUV blank, which is significantly more complex to build than an optical blank, given more stringent requirements for flatness, defectivity and absorber film quality,” said James Westphal, director of marketing at KLA-Tencor.

There are two types of defects in EUV blanks—amplitude and phase. Amplitude defects are surface particles and pits, which can cause contrast changes. Phase defects are bumps and pits that are buried in the stack, which can cause phase changes.

Fortunately, the industry has developed mask blank inspection tools capable of locating defects. Then, chipmakers have found ways to circumvent the defect problems.

In the flow, the defect is marked and covered by an absorber. The blank is then shipped to the mask vendor. From there, the e-beam patterns the mask, but it avoids the defect using pattern shifting techniques.

Generally, meanwhile, today’s EUV blanks range from products with less stringent defect specs for R&D purposes to production-grade quality with fewer defects.

There is an ample supply of EUV mask blanks with less stringent specs, but products with tighter defect specifications is a different story. These EUV blanks are far from perfect, although they are good enough for the production planned for EUV in the short term, analysts said.

“Multilayer defects, unlike absorber defects on optical and EUV masks, cannot be repaired,” HJL’s Levinson said. “A few multilayer defects can be tolerated if all are sufficiently small. A few defects can be covered by the absorber in the patterned mask and therefore don’t lead to printed defects.”

The problem is that there may not be enough EUV blanks with lower defect specs in the market, especially when EUV lithography ramps up.

Prices are another issue. An EUV blank with tight specs and actinic inspections cost more than $100,000 each, roughly 10 times more expensive than an optical blank, analysts said. However, a blank with less stringent specs costs far less than $100,000, analysts said.

That’s just the price for the blank, and it doesn’t account for the overall cost of an EUV photomask, which is expected to be expensive.

Who’s doing what?
In response, suppliers of EUV blanks are ramping up production with plans to meet the quality and price demands in the industry.

Recently, AGC expanded its EUV mask blank production in Japan. Meanwhile, Hoya makes EUV mask blanks and mature optical blanks in Japan, while its Singapore site makes advanced optical blanks.

Hoya now plans to install a high-volume manufacturing line for EUV blanks in Singapore. “Hoya is scaling capacity to align with customer roadmaps, and has announced plans for a new production facility in Singapore,” said Damian Thong, an analyst at Macquarie Group.

The current demand for EUV blanks is a mixed picture. So far, Hoya is seeing more demand for R&D blanks with less stringent specs. “At this point, the demand for engineering and evaluation blanks with less stringent defect specifications is still very heavy, and actually a high percentage of the overall demand,” Hoya’s Akiki said.

For some time, Hoya has been in production and can produce blanks with tighter defect specs. “Our current EUV blanks are the world’s best and are being used and evaluated by every company using EUV. We will continue to drive down the defect levels, of course, as we go forward,” Akiki said. “As volumes grow and yields increase, market forces will dictate the price. But historically, prices have come down from initial offerings as the technology matures. That will need to be balanced against the continuing investments needed.”

Meanwhile, Applied Materials is developing next-generation EUV mask blanks in a facility in Singapore. It’s unclear if it will field a current-generation product.

“What is Applied Materials doing in that direction to drive some of this materials innovation? We are looking at it from a holistic perspective,” Applied’s Jindal said.

Applied wants to re-engineer the EUV blank. For example, the backside of an EUV blank is based on a chrome nitride material. But for next-generation blanks, the backside requires harder materials to reduce defects.

“We have a chrome nitride variation,” Jindal said. “It shows a higher critical load, which means it can have higher hardness, leading to a lower defect generation.”

Then, for next-gen blanks, the multilayer silicon/molybdenum stack requires better interfaces. “We have looked at controlling these interfaces by changing the hardware and process technology in a way we can get sharper interfaces. That interface engineering leads to high reflectivity,” he said.

Applied and others are also working on reducing the thickness of the absorber, which will mitigate unwanted 3D mask effects.

To be sure, chipmakers would like to see more competition in the EUV blank business. It could help boost quality and reduce prices.

The problem is that there are only a few chipmakers that are inserting EUV, meaning there is a limited customer base for blank suppliers. This is already a shaky business model in a tough business environment.


Related Stories:

EUV’s New Problem Areas

EUV Pellicle, Uptime And Resist Issues Continue

Next EUV Issue: Mask 3D Effects


David Pinto says:

3D mask effects are a key consideration too. Further reduction in printed features and half pitch will require absorber layers to be reduced by more than half the thickness to avoid shadowing effects on the photomask that caused mask 3D effects. Innovation in both deposition and etch for the new absorber materials such as Ni, Co and other alloys have the potential to replace TaN as thinner TaN reduces absorption. Shadowing effects will get even more critical for future high NA scanners with the larger angle of incidence required for 5nm node and beyond. I’m no expert, but will point to guys like Meng Lee who can elucidate more clearly on EUV Mask Blanks challenges and solutions !

Daniel Thomas says:

“Meanwhile, in a major milestone, Samsung became the industry’s first chipmaker to put EUV into production. EUV is being used for 7nm.”

Is that why Samsung just announced (Nov 14) their next flagship S10 series (Exynos 9820) will be manufactured using 8nm LPP FinFET process, NOT 7nm?

Also, suspiciously there are no 9820 benchmarks yet.

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