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Week In Review: Manufacturing, Test


Government funding President Biden signed the CHIPS and Science Act into law on Tuesday, saying “America is back and leading the way.” That same day Micron touted a $40 billion investment through to 2030, which it expects will create 40,000 American jobs. “This legislation will enable Micron to grow domestic production of memory from less than 2% to up to 10% of the global market in t... » read more

Hybrid Bonding Moves Into The Fast Lane


The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

Week In Review, Manufacturing, Test


The U.S. is attempting to restrict sales of ASML’s deep ultra-violet (DUV) litho systems to China, according to a report from Bloomberg. The U.S. has been working to limit China's access to advanced technology for some time, and it has already limited sales of extreme ultra-violet (EUV), which is used to develop chips at the most advanced process nodes. DUV, in contrast, is used for older-nod... » read more

Week In Review: Manufacturing, Test


Notes from the fabs Intel warned the “scope and pace" of the Ohio fab buildout could be impacted due to U.S. Congress’ inaction on funding the $52 billion CHIPS Act. The facility was announced in January with an initial phase investment of more than $20 billion with a larger expansion up to $100 billion over the next decade. The initial phase is not expected to be impacted, other than a de... » read more

High-NA EUV May Be Closer Than It Appears


High-NA EUV is on track to enable scaling down to the Angstrom level, setting the stage for chips with even higher transistor counts and a whole new wave of tools, materials, and system architectures. At the recent SPIE Advanced Lithography conference, Mark Phillips, director of lithography hardware and solutions at Intel, reiterated the company’s intention to deploy the technology in high... » read more

Shortages Spark Novel Component Lifecycle Solutions


The semiconductor industry’s supply chain problems are prompting some innovative solutions and workarounds, and while they don't solve all problems, they are improving efficiency and extending equipment lifetimes. The shortages, which affect everything from the chips used in automotive, IoT, and consumer ICs to the equipment used to manufacture and test them — span global supply lines. T... » read more

A Guide To Fast Optimal Solutions To Complex Problems For Quantum Computers


Most people have already heard the term “quantum computer.” There has been a lot of interest in quantum computers over the last few years, with great expectations that they will dramatically change the world soon. These days, we use computers all the time in our daily lives. Personal computers and smartphones are obvious computers, but there are many more computers hidden in plain sight aro... » read more

Week In Review: Manufacturing, Test


The U.S. Senate approved the 2022 America COMPETES act, which has big ramifications for the chip industry. The bill now heads to the House for further reconciliation. If approved, it would provide more than $50 billion in U.S. subsidies for semiconductor chip manufacturing. The SIAC (Semiconductor In America Coalition) urged Congress to act promptly to achieve a bipartisan compromise soon and o... » read more

Highly Selective Etch Rolls Out For Next-Gen Chips


Several etch vendors are starting to ship next-generation selective etch tools, paving the way for new memory and logic devices. Applied Materials was the first vendor to ship a next-gen selective etch system, sometimes called highly-selective etch, in 2016. Now, Lam Research, TEL, and others are shipping tools with highly-selective etch capabilities, in preparation for futuristic devices su... » read more

Extending Copper Interconnects To 2nm


Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

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