EUV Arrives, But More Issues Ahead

EUV has arrived. After decades of development and billions of dollars of investment, EUV lithography is taking center stage at the world’s leading fabs.

More than 20 years after ASML’s extreme ultraviolet lithography research program began, and nearly a decade after its first pre-production exposure tools, the company expects to deliver 30 EUV exposure systems in 2019. That is nearly double the installed base for this technology, and it moves the needle forward for device scaling.

The focus now shifts to the many process optimization challenges that remain. The challenges of extreme scaling and the potential advantages of EUV technology are well known at this point. For several years, gate scaling has been limited by transistor electrostatics. To increase circuit density, manufacturers have turned to smaller contacts and tighter contact pitch. Placement and sidewall profiles have become more critical, even as the complex multi-patterning schemes used to extend 193-nm lithography have eroded error budgets and process margin.

EUV promises improved resolution with a simpler process flow and less restrictive design rules. For sub-7 nm devices, it offers a clear cost advantage, according to Ryoung-Han Kim, group manager at Imec, in a presentation at the recent SPIE Advanced Lithography Conference.

Yet EUV is only beginning to come into its own as a manufacturing technology. Equipment downtime and defect levels remain high. Such fundamental topics as the interactions between EUV photons and photoresist still require thorough investigation. And much work remains as the industry seeks to optimize EUV-centric process flows.

As in earlier lithography generations, EUV faces tradeoffs among resolution, line edge roughness, and exposure dose. Chris Mack, CTO of Fractilia, explained that EUV offers a 2.5X resolution improvement over leading edge 193nm exposures, increasing pixel density by a factor of 6. While it currently increases pixel throughput by about 2X, both resolution and throughput are potentially limited by line edge roughness. Over several technology generations, the magnitude of line edge roughness has remained constant as overall feature dimensions have shrunk. Roughness now appears to be the limiting factor for overall resolution improvement.

Line edge roughness is closely related to process variability. Current EUV illumination sources produce 14 times fewer photons than their 193nm counterparts. The random distribution of these photons (so-called “shot noise”) can leave some areas with insufficient exposure.

While increasing exposure dose can increase throughput and reduce underexposure-related defects, it also can make overexposure-related defects worse. Individual resist molecules likewise have dimensions comparable to the required feature sizes. The random distribution of photoacid and polymer molecules introduces noise into the captured areal image.

Finally, the scanning electron microscopes used to inspect resist features are approaching their own resolution limits, obscuring the actual resist pattern with measurement error. As EUV matures, manufacturers must differentiate between variability that is inherent in the physics of lithography, and variation that simply indicates a poorly controlled process.

From light sources to photomasks: pattern definition
Despite their limitations, CD-SEMs still offer the best available combination of speed, accuracy, and ease of use for manufacturing applications. In the absence of alternative technologies, smart sampling can help differentiate among the effects of metrology error, exposure noise, and resist inhomogeneity, said Gian Lorusso, an Imec scientist. If the same location is measured twice, differences between the two measurements can be attributed to SEM noise. Measuring the same location twice on two different dice gives a combination of shot noise and SEM noise. Making two measurements of two dies on two different wafers, in turn, makes it possible to decompose the total error into resist error, shot noise, and SEM noise components.

Programmed “anchor” defects ensured that such repeated measurements were positioned correctly. Lorusso’s group found good agreement between decomposition analysis based on wafer data and power spectral density analysis of mask data. They were able to conclude that increases in roughness between the mask and the wafer were not due to mask defects. Rather, SEM noise was a major contributor to observed “roughness” in line and space patterns, while EUV shot noise mattered more for contact holes.

More source brightness, bigger optics
The relative dimness of EUV light sources has been an issue since the inception of the technology. While 193nm illumination comes directly from ArF lasers, EUV photons are emitted from a plasma created by superheated tin droplets. A 20kW laser might be used to generate the plasma, but only 250W or less of 13.5nm radiation is actually captured by the collector optic. The Mo/Si multilayer mirrors that make up the optical path absorb even more; only a small fraction of the source brightness is actually delivered to the photoresist. Igor Fomenkov at ASML said the company is now shipping 250W sources and has demonstrated 450W illumination in brief bursts, while Gigaphoton’s Hakaru Mizoguchi said his company expects to reach 330W of source power by the end of 2019.

Meanwhile, 0.55 numerical aperture exposure systems seek to use the available photons more effectively. A larger numerical aperture focuses light from a wider range of angles, improving resolution at the cost of reduced depth of field. Incoming photons strike the mask at a shallower incident angle, leading to shadowing and undesirable edge effects. The problem is particularly acute for reflective optics like those used in EUV, where inbound and outbound beams can cross and the mask edge can interact with both.

Research to identify alternative absorber materials to reduce these effects is under way, but high-NA optics will make the issue worse. Increasing the lens magnification reduces shadowing effects, said Jan van Schoot, senior principal architect at ASML. He noted that can dramatically degrade throughput unless the mask size also increases.

The proposed 0.55 NA optics would address this issue by using 8X/4X anamorphic lenses, applying the higher magnification only in the scanning direction. This design cuts the exposure field size in half, an improvement over the 0.25X field size of a round 8X optic, but still poses throughput challenges. To reduce overhead due to wafer and reticle moves, ASML’s proposed system would expose the first half-field on all wafers in a single lot, storing the results in an onboard stocker, then expose the second half-field.

Better mask models, better targeting
The exposure system optics and the photomask are jointly responsible for supplying an accurate image at the photoresist. “Accurate” in this context means both a true representation of the image specified by the design, and an illumination profile that is centered on the specified features. While masks have needed to account for edge effects and proximity effects for years, the correction models appropriate for EUV are still evolving.

Chris Progler, CTO of Photronics, observed a large increase in defect levels with a relatively small change in line pitch, from 32nm to 30nm. This kind of behavior is often a sign that the system is near the threshold of printability. In one test, the mask produced by a standard optical proximity correction model resulted in seemingly random line breaks in the resist image.

Line breaks often are due to stochastic resist effects, such as diffusion of photoacid from exposed to unexposed areas, but attributing this specific case to inherent limitations seems to be premature. Simulations based on the mask contour, rather than the design, more accurately predicted wafer results, Progler said.

Better simulations allowed researchers to more accurately target the desired illumination profile and eliminate the line break defects.

Resists, defects, and pattern capture
Once the optical system supplies the desired illumination profile, the photoresist is responsible for capturing it as a physical pattern that can be transferred to the wafer. EUV resists face a number of challenges due, again, to the relatively low number of available photons. They must be sensitive enough to capture the image, but at the same time high aspect ratio wafer structures require longer etch times and therefore better etch resistance from the photoresist. Thin resist layers are preferable because tall, narrow resist pillars tend to simply fall over. The downside is that thinner resists capture fewer photons and are more susceptible to erosion during the etch.

In light of these challenges, the industry is considering alternatives to the chemically amplified resists used in existing lithography processes. In a chemically amplified resist, each incident photon may generate several photoacid molecules. Each photoacid molecule, in turn, “deprotects” a resist polymer molecule, rendering it soluble in developer. The “sensitivity” of the resist is a measure of the number of photoacid molecules generated by each photon. The diffusion of photoacid molecules away from the point where they were generated is critical for successful amplification, but also leads to image blur when photoacid diffuses beyond the boundaries of the exposed area.

The most widely studied alternative to chemically amplified resist depends on metal oxide clusters surrounded by an organic shell. Though the inorganic core provides EUV absorption and etch resistance, the organic shell defines the processability of the film. Lianjia Wu, a researcher at the Advanced Research Center for Nanolithography, pointed out that the organic shell is what actually dissolves in developer or cross links with adjacent molecules. Small changes to the organic shell improved performance of both zirconium and hafnium cluster-based photoresists.

Another approach, demonstrated at Imec, infiltrates alumina into the resist after exposure and before etch. The idea is to separate the pattern capture and pattern transfer roles, optimizing for each separately.

C. Grant Willson, chairman of the Department of Chemical Engineering at the University of Texas at Austin, proposed a third approach based on an “unzipping” polymer that depolymerizes on exposure to radiation. EUV photons have much more energy due to their short wavelength, and as a result cause a cascade of secondary electron emissions when they interact with resist. In Willson’s proposed material, each radiochemical interaction can break many covalent bonds, demonstrating the gain required for adequate sensitivity. The unzipping reaction is confined to a single polymer chain, though, and does not depend on the diffusion of a photoacid catalyst. Without photoacid diffusion, there is no associated image blur.

Managing defects for manufacturability
Regardless of the chemistry involved, the failure-free window is one measure of the manufacturability of a resist process. As lines get closer together and line edge roughness increases, eventually microbridges form between adjacent lines. If these persist through the etch process they become short circuits. The smallest spacing at which the number of microbridges remains below a desired defect threshold is the minimum manufacturable dimension.

At the other extreme, as spaces get wider and the lines between them get narrower, eventually line breaks appear. These become open circuits in the finished device. This side of the failure-free window is defined by the minimum line width at which the number of breaks falls below the desired threshold. In a contact hole array, the failure-free window lies between the smallest holes that are still open, and the largest holes that can be printed without merging with their neighbors. A manufacturable process typically has a so-called “stochastic cliff” on either side of the failure-free window, beyond which the number of observed failures drops sharply.

Figure: Stochastic cliffs and failure-free window as a function of mean CD. Source: Imec.

Because of the sheer number of vias in a modern GPU or CPU, the defect threshold is very low. Such chips can have more than 100 km of interconnect wiring, according to Dustin Janes, an applications engineer at SCREEN. Failed vias at even the one part per billion level can cut yield by 25%. In a well-behaved process, almost all features will fall within a tight distribution around the average CD. Still, the average CD alone is not enough to characterize the process yield. The “tails” of the device distribution matter, too.

These tails contain rare events by definition. They are difficult to define, with results highly dependent on the number of measurements. However, Imec researcher Peter De Bisschop pointed out that simply extrapolating the number of defects to zero as CD increases (or decreases, at the other side of the window) is not sufficient. Not all defect distributions are Gaussian. In some cases, there is a defect “floor,” at which the failure rate is non-zero but independent of feature dimensions.

It’s generally agreed that these defects are stochastic in nature, but it’s not clear exactly which aspect of the process is responsible for them. A microbridge forms when the resist between two adjacent lines fails to dissolve. Anuja De Silva, technical project lead for patterning materials and process technology at IBM, questioned whether the exposure did not supply enough photons to clear the bridge, or whether the resist solubility was too low.

Not all process parameters are equally easy to adjust. Increasing the exposure dose to prevent microbridges is extremely challenging and may also increase the number of line breaks as photons in the tails of the illumination profile fall outside the desired features. Increasing the photoacid concentration can lead to increased diffusion and blur; adding more base quencher can cause miscibility and inhomogeneity issues.

Understanding resist behavior
While resist sensitivity plays a role, resists with the same sensitivity do not necessarily have the same failure-free window or defect distribution. Investigating the problem systematically, Ivan Pollentier’s group at Imec used residual gas analysis to track the species evolving from the exposed resist surface and obtain a measure of the number of chemical reactions as a function of exposure dose. While RGA cannot measure photoacid generation directly, it can differentiate between the polymer deprotection reaction and photon-induced scission reactions. Contrast curves reflect the change in resist solubility with exposure dose. Combining this information with simulations of the deprotection and diffusion processes inside the resist layer allowed them to extract the rate of change of photoacid generation as a function of exposure dose, which appeared to be most closely correlated with the resist failure curve.

Post-resist processing and pattern transfer
The features which ultimately appear on the wafer are the result of the exposure system’s interaction with the photoresist, but also of such factors as the etch profile, deposition uniformity, and wafer stress. Generally speaking, it is easier to change the resist and pattern transfer processes than the exposure system. It is easier to introduce a self-assembled monolayer or improve post-etch residue removal than it is to increase the useful output of a laser-produced plasma. Often, post-lithography processing can repair resist defects left behind by the exposure step. If a contact hole is partially blocked by insoluble resist, a less selective etch might succeed in opening it.

Post-exposure processing can also reveal problems with the resist chemistry or the resist/wafer interaction. Hidetami Yaegashi, senior manager at Tokyo Electron, found that vias which appeared to be open during the CD-SEM inspection were still not accurately transferred to the wafer. Resist in contact with the wafer was less soluble than the bulk. Post-develop vias still had resist material at the bottom, causing incomplete etching. The addition of a post-develop de-scumming step appeared to resolve the problem.

Feature tuning with self-assembled monolayers
First considered for use in 193nm resolution enhancement schemes, directed self-assembly remains relevant in the EUV lithography era. Directed self-assembly uses a prepared surface to attract one end of a block copolymer, while the other end provides etch resistance or some other functionality.

Stacey Bent, a chemical engineering professor at Stanford University, explained that selective deposition potentially can reduce the number of lithography steps. Alignment error accumulates with each exposure step, so reducing the number of steps should recover process margin. For example, an inhibiting layer might be used to prevent atomic layer deposition on some areas, or it might be etched away to lift off deposition defects.

Self-assembly is an energy minimization process. The block copolymers will form the configuration with the lowest surface energy, limited only by their movement kinetics. Gradual contours are typically more energetically favorable than sharp discontinuities. A self-assembled monolayer deposited on an array of contact holes should make the holes smaller and more uniform, said Charlie Liu, research staff member at IBM. On sidewalls, it can help make etch profiles more vertical. It can thus be an important tool in post-lithography efforts to improve pattern transfer and reduce edge placement error.

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