tag: line-edge roughness

Measuring 3D Sidewall Topography & LER for Photoresist Patterns Using Tip-Tilting AFM Technology
By Technical Paper Link - 19 Feb, 2023 - Comments: 0

A new technical paper titled "Enhancing the precision of 3D sidewall measurements of photoresist using atomic force microscopy with a tip-tilting technique" by researchers at National Metrology Institute of Japan (NMIJ) and National Institute of Advanced Industrial Science and Technology (AIST). "We have developed a technique for measuring the sidewall of the resist pattern using atomic for... » read more

Looking Forward To SPIE, And Beyond
By Katherine Derbyshire - 16 Feb, 2023 - Comments: 0

On the eve of this year’s SPIE Advanced Lithography + Patterning conference, I took a look at the IEEE Devices and Systems Roadmap’s lithography section. It’s especially notable for the emergence of EUV lithography, which has quickly become critical for advanced logic. High-NA tools to support still smaller dimensions are on the horizon. In the near-term, though, the key challenge is not ... » read more

How Does Line Edge Roughness (LER) Affect Semiconductor Performance At Advanced Nodes?
By Yu De Chen - 26 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. This is demonstrated in figure 1, which displays a simulation of line resistance vs. line CD across different BEOL metals. Even without... » read more

A Study Of The Impact Of Line Edge Roughness On Metal Line Resistance Using Virtual Fabrication
By Coventor - 15 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor limiting chip operation speeds at advanced nodes. This is because smaller metal line pitches require narrower line CD and line-to-line spacing, which introduces higher metal line resistance and line-to-line capacitance. A surface scattering effect is the root cause for the exponentially increased metal resistivity at smaller metal line pitch... » read more

Advantages Of Measuring Surface Roughness With White Light Interferometry
By Bruker - 09 Aug, 2022 - Comments: 0

The concept of measuring surface roughness originated nearly a century ago as a means to prevent uncertainty and disputes between manufacturers and buyers. Now, it has become a common identifier used throughout industry for validating manufacturing processes, confirming adherence to both internal and regulatory specifications, and guaranteeing quality and performance of end products. Subjective... » read more

Strategies For Faster Yield Ramps On 5nm Chips
By Laura Peters - 12 Apr, 2022 - Comments: 0

Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

Finding, Predicting EUV Stochastic Defects
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Several vendors are rolling out next-generation inspection systems and software that locates problematic defects in chips caused by processes in extreme ultraviolet (EUV) lithography. Each defect detection technology involves various tradeoffs. But it’s imperative to use one or more of them in the fab. Ultimately, these so-called stochastic-induced defects caused by EUV can impact the perf... » read more

Inspecting, Patterning EUV Masks
By Mark LaPedus - 06 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Effects Of A Random Process Variation On The Transfer Characteristics Of A Fundamental Photonic Integrated Circuit Component
By Coventor - 18 Sep, 2019 - Comments: 0

Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS pr... » read more

Target: 50% Reduction In Memory Power
By Brian Bailey - 11 Apr, 2019 - Comments: 3

Memory consumes about 50% or more of the area and about 50% of the power of an SoC, and those percentages are likely to increase. The problem is that static random access memory (SRAM) has not scaled in accordance with Moore's Law, and that will not change. In addition, with many devices not chasing the latest node and with power becoming an increasing concern, the industry must find ways to... » read more

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