Metrology Challenges For Gate-All-Around


Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

Making Chips At 3nm And Beyond


Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

How And Where ML Is Being Used In IC Manufacturing


Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. Part one ... » read more

Week In Review: Manufacturing, Test


SPIE At the SPIE Advanced Lithography conference, Lam Research has introduced a new dry resist technology for extreme ultraviolet (EUV) lithography. Dry resist technology is a new approach to deposit and develop EUV resists. It is a dry deposition technique with alternate compositions and mechanisms. By combining Lam’s deposition and etch process expertise with partnerships with ASML a... » read more

Clean Focus, Dose And CD Metrology For CD Uniformity Improvement


Authors: Honggoo Leea, Sangjun Hana, Minhyung Honga, Seungyong Kima, Jieun Leea, DongYoung Leea, Eungryong Oha, Ahlin Choia, Nakyoon Kimb, John C. Robinsonc, Markus Mengelc, Pablo Rovirac, Sungchul Yooc, Raphael Getinc, Dongsub Choib, Sanghuck Jeonb aSK Hynix, 2091, Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do, 467-701, Korea bKLA-Tencor Korea, Starplaza bldg., 53 Metapolis-ro, Hwasung... » read more

3D NAND Metrology Challenges Growing


3D NAND vendors face several challenges to scale their devices to the next level, but one manufacturing technology stands out as much more difficult at each turn—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems and ensure yields for all chip types. In the case of 3D NAND, the metrology tools are becoming more expensive at each iteration... » read more

EUV Arrives, But More Issues Ahead


EUV has arrived. After decades of development and billions of dollars of investment, EUV lithography is taking center stage at the world’s leading fabs. More than 20 years after ASML's extreme ultraviolet lithography research program began, and nearly a decade after its first pre-production exposure tools, the company expects to deliver 30 EUV exposure systems in 2019. That is nearly doubl... » read more

E-Beam Review And CD Measurement Revolutionizes Display Yield Management


Fundamental changes are occurring in the display industry, driven by demands for higher-resolution screens and other capabilities for both mobile and TV applications. To meet these demands, the display technology roadmap in this article calls for innovations in materials, processes and device technology. Critical requirements include smaller design rules and the adoption of a range of materi... » read more

Finding Defects In Chips With Machine Learning


Chipmakers are using more and different traditional tool types than ever to find killer defects in advanced chips, but they are also turning to complementary solutions like advanced forms of machine learning to help solve the problem. A subset of artificial intelligence (AI), machine learning has been used in computing and other fields for decades. In fact, early forms of machine learning ha... » read more

In-Cell Overlay Metrology By Using Optical Metrology Tool


By Honggoo Lee, Sangjun Han, Minhyung Hong, Seungyong Kima, Jieun Lee, DongYoung Leea, Eungryong Oh, and Ahlin Choi of SK Hynix, and Hyowon Park, Waley Liang, DongSub Choi, Nakyoon Kim, Jeongpyo Lee, Stilian Pandev, Sanghuck Jeon, John C. Robinson of KLA-Tencor Abstract Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced s... » read more

← Older posts