tag: deposition

Reflectometry-Based Technique for Characterising Complex Thin-Film Structures (Aalto U. et al.)
By Technical Paper Link - 28 Apr, 2026 - Comments: 0

A new technical paper, "Characterisation of Complex Multilayer Nanostructures with High Aspect Ratio," was recent published by researchers at Aalto University, University of Eastern Finland, Chipmetrics OY, and VTT MIKES. Abstract "Deposition studies of deep vertical dips on semiconductor wafers can create problems at an industrial manufacturing scale, since cross-sectioning requires a lo... » read more

When Semiconductor Materials Misbehave
By Gregory Haley - 27 Apr, 2026 - Comments: 0

Key Takeaways Material behavior in production depends on the process context that no development environment can fully replicate. In advanced packaging, the interactions that cross domain boundaries are increasingly where failures originate. The most accurate materials data is also the most commercially sensitive, leaving simulation models calibrated against generic inputs rather tha... » read more

Every Atom Now Counts In Advanced Chip Manufacturing
By Gregory Haley - 22 Jan, 2026 - Comments: 0

Artificial-intelligence workloads are pushing semiconductor design to a point where traditional scaling strategies are running out of room. Performance improvements that once came from shrinking transistors now depend increasingly on how devices are stacked, interconnected, and isolated. Transistor scaling still matters, but advanced device architectures no longer can accommodate the power dens... » read more

What’s Next For Through-Silicon Vias
By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Defect Challenges Grow At The Wafer Edge
By Laura Peters - 10 Sep, 2024 - Comments: 0

Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly repercussions that span multiple processes and multi-chip packages. This is made more difficult by the widespread rollout of such processes as hybrid bonding, which require pristine surfaces, and the gro... » read more

Research Bits: Aug. 27
By Jesse Allen - 27 Aug, 2024 - Comments: 0

Ammonia-free GaN Researchers from Nagoya University discovered a way to grow gallium nitride (GaN) semiconductors without using ammonia. The process is both more environmentally friendly and allows for high-quality growth of crystals at a lower cost. Metal organic chemical vapor deposition (MOCVD) is the most common technique for GaN production, which uses ammonia (NH3) gas as the source of... » read more

Single Vs. Multi-Patterning Advancements For EUV
By Gregory Haley - 20 Jun, 2024 - Comments: 0

As semiconductor devices become more complex, so do the methods for patterning them. Ever-smaller features at each new node require continuous advancements in photolithography techniques and technologies. While the basic lithography process hasn’t changed since the founding of the industry — exposing light through a reticle onto a prepared silicon wafer — the techniques and technology ... » read more

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors
By James Kim - 22 Feb, 2024 - Comments: 0

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during any number of process steps. In this article, I want to share a different mechanism that can cause wafer defects. Namely, that these defects can be structural defects that are caused by a biased dep... » read more

Metal Films On 2D Materials: vdW Contacts And Raman Enhancement (University of Cambridge)
By Technical Paper Link - 14 Feb, 2024 - Comments: 0

A technical paper titled “Metal Films on Two-Dimensional Materials: van der Waals Contacts and Raman Enhancement” was published by researchers at University of Cambridge. Abstract: "Electronic devices based on two-dimensional (2D) materials will need ultraclean and defect-free van der Waals (vdW) contacts with three-dimensional (3D) metals. It is therefore important to understand how vdW ... » read more

Semiconductor Device Manufacturing Process Challenges And Opportunities
By Andreas Bier - 07 Dec, 2023 - Comments: 0

Semiconductor device manufacturing involves a complex series of processes that transform raw materials into finished devices. The process typically involves four major stages: wafer fabrication, wafer testing, assembly or packaging, and final testing. Each stage has its own unique set of challenges and opportunities. The semiconductor device manufacturing process faces several challenges, inclu... » read more

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