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Nudging 2D semiconductors forward


The buzz about 2D materials replacing silicon appears to be premature. While 2D semiconductors have emerged as potential successors, it's not clear when or even if that will happen. As Iuliana Radu, Imec's director of quantum and exploratory computing observed, the “end” of silicon has been predicted many times before. It is not clear when 2D semiconductors will need to be ready. In fac... » read more

Stacked Nanosheets And Forksheet FETs


What comes next after gate-all-around FETs is still being worked out, but it likely will involve some version of stacked nanosheets. The design of advanced transistors is a tradeoff. On one hand, it takes less gate capacitance to control a thin channel. On the other hand, thin channels can’t carry as much drive current. Stacked nanosheet designs seek to reconcile these two objectives by... » read more

Thinner Channels With 2D Semiconductors


Moving to future nodes will require more than just smaller features. At 3/2nm and beyond, new materials are likely to be added, but which ones and exactly when will depend upon an explosion of material science research underway at universities and companies around the globe. With field-effect transistors, a voltage applied to the gate creates an electric field in the channel, bending the ban... » read more

Demand, Lead Times Soar For 300mm Equipment


A surge in demand for various chips is causing select shortages and extended lead times for many types of 300mm semiconductor equipment, photomask tools, wafers, and other products. For the last several years, 200mm equipment has been in short supply in the market, but issues are now cropping up throughout the 300mm supply chain, as well. Traditionally, lead times have been three to six mont... » read more

Applications, Challenges For Using AI In Fabs


Experts at the Table: Semiconductor Engineering sat down to discuss chip scaling, transistors, new architectures, and packaging with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fujimura, CEO of D2S. Wh... » read more

Upturn Seen In Semi Equipment Biz


Business continues to get better in the semiconductor equipment sector. VLSI Research, for one, has raised its forecast in the arena. But there is still some uncertainty amid mixed growth for semiconductors, trade wars and other factors. After a downturn in 2019, the semiconductor equipment market expected an upturn in 2020. Then, the Covid-19 pandemic struck. Suddenly, a large percentage... » read more

Atomic Layer Etch Expands To New Markets


The semiconductor industry is developing the next wave of applications for atomic layer etch (ALE), hoping to get a foothold in some new and emerging markets. ALE, a next-generation etch technology that removes materials at the atomic scale, is one of several tools used to process advanced devices in a fab. ALE moved into production for select applications around 2016, although the technolog... » read more

Making Chips At 3nm And Beyond


Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Inspecting, Patterning EUV Masks


Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Intra-Field Stress Impact on Global Wafer Deformation


One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., thermal expansion coefficients) may result in process-induced warpage of the wafers at room temperature. When these warped wafers are loaded onto the scanner for the next layer exposure, in-plane disto... » read more

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